[PATCH] D16829: An implementation of Swing Modulo Scheduling

[Brendon Cahoon via llvm-commits]

bcahoon added a comment.

In http://reviews.llvm.org/D16829#460066, @marksl wrote:

> After ISEL our compare instructions, multiply, and MAC instructions have real physical register side effects. I'm getting errors from SWP for loops containing these physical register dependencies. Are you aware of this? Is there a way to model physical register dependencies with loop carried dependencies such that we would generate correct code for them?


Hi Mark - yes, I am aware of the of the problem, but don't yet have a good fix for it.  One potential fix is to not pipeline loops that end up with a loop carried physical register.  That's what's I've added to my local version.  I added the following function, which is called from schedulePipeline() if a schedule is found.

bool SMSchedule::isValidSchedule(SwingSchedulerDAG *SSD) {

  const TargetRegisterInfo *TRI = ST.getRegisterInfo();
  for (int i = 0, e = SSD->SUnits.size(); i < e; ++i) {
    SUnit &SU = SSD->SUnits[i];
    if (!SU.hasPhysRegDefs)
      continue;
    int StageDef = stageScheduled(&SU);
    assert(StageDef != -1 && "Instruction should have been scheduled.");
    for (auto &SI : SU.Succs)
      if (SI.isAssignedRegDep())
        if (TRI->isPhysicalRegister(SI.getReg()))
          if (stageScheduled(SI.getSUnit()) != StageDef)
            return false;
  }
  return true;

}


http://reviews.llvm.org/D16829