[PATCH] D21215: [docs] Update AMDGPU relocation information

[Rafael Espíndola via llvm-commits]

Lgtm
On Jun 13, 2016 6:05 PM, "Konstantin Zhuravlyov" <kzhuravl_dev at outlook.com>
wrote:

> kzhuravl updated the summary for this revision.
> kzhuravl updated this revision to Diff 60617.
> kzhuravl added a comment.
>
> Added back R_AMDGPU_ABS32_LO, also added R_AMDGPU_ABS32
>
>
> http://reviews.llvm.org/D21215
>
> Files:
>   docs/CodeGenerator.rst
>
> Index: docs/CodeGenerator.rst
> ===================================================================
> --- docs/CodeGenerator.rst
> +++ docs/CodeGenerator.rst
> @@ -2672,25 +2672,26 @@
>    byte alignment. These values use the same byte order as other word
> values in
>    the AMD GPU architecture
>
> -Following notations are used for specifying relocation types
> +Following notations are used for specifying relocation calculations:
>
>  * **A** --- Represents the addend used to compute the value of the
> relocatable
>    field
> +* **P** --- Represents the place (section offset or address) of the
> storage unit
> +  being relocated (computed using ``r_offset``)
>  * **S** --- Represents the value of the symbol whose index resides in the
>    relocation entry
>
>  AMDGPU Backend generates *Elf64_Rela* relocation records with the
> following
>  supported relocation types:
>
> -  ====================  =====  ==========  ============================
> -  Relocation type       Value  Field       Calculation
> -  ====================  =====  ==========  ============================
> -  ``R_AMDGPU_NONE``     0      ``none``    ``none``
> -  ``R_AMDGPU_32_LOW``   1      ``word32``  (S + A) & 0xFFFFFFFF
> -  ``R_AMDGPU_32_HIGH``  2      ``word32``  ((S + A) >> 32) & 0xFFFFFFFF
> -  ``R_AMDGPU_64``       3      ``word64``  S + A
> -  ``R_AMDGPU_32``       4      ``word32``  S + A
> -  ====================  =====  ==========  ============================
> -
> -Only R_AMDGPU_32_LOW and R_AMDGPU_32_HIGH can be handled by the
> -dynamic linker.  The rest must be statically resolved.
> +  =====================  =====  ==========  ====================
> +  Relocation type        Value  Field       Calculation
> +  =====================  =====  ==========  ====================
> +  ``R_AMDGPU_NONE``      0      ``none``    ``none``
> +  ``R_AMDGPU_ABS32_LO``  1      ``word32``  (S + A) & 0xFFFFFFFF
> +  ``R_AMDGPU_ABS32_HI``  2      ``word32``  (S + A) >> 32
> +  ``R_AMDGPU_ABS64``     3      ``word64``  S + A
> +  ``R_AMDGPU_REL32``     4      ``word32``  S + A - P
> +  ``R_AMDGPU_REL64``     5      ``word64``  S + A - P
> +  ``R_AMDGPU_ABS32``     6      ``word32``  S + A
> +  =====================  =====  ==========  ====================
>
>
>
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