[llvm] r272512 - Pass DebugLoc and SDLoc by const ref.
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 12 11:32:11 PDT 2016
Hey, awesome. Thanks!
On Sun, Jun 12, 2016, 8:45 AM Benjamin Kramer via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: d0k
> Date: Sun Jun 12 10:39:02 2016
> New Revision: 272512
>
> URL: http://llvm.org/viewvc/llvm-project?rev=272512&view=rev
> Log:
> Pass DebugLoc and SDLoc by const ref.
>
> This used to be free, copying and moving DebugLocs became expensive
> after the metadata rewrite. Passing by reference eliminates a ton of
> track/untrack operations. No functionality change intended.
>
> Modified:
> llvm/trunk/include/llvm/CodeGen/FastISel.h
> llvm/trunk/include/llvm/CodeGen/GCMetadata.h
> llvm/trunk/include/llvm/CodeGen/MachineFunction.h
> llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> llvm/trunk/include/llvm/CodeGen/SelectionDAGTargetInfo.h
> llvm/trunk/include/llvm/Target/TargetInstrInfo.h
> llvm/trunk/include/llvm/Target/TargetLowering.h
> llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
> llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.h
> llvm/trunk/lib/CodeGen/GCRootLowering.cpp
> llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp
> llvm/trunk/lib/CodeGen/MachineFunction.cpp
> llvm/trunk/lib/CodeGen/MachineInstr.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/lib/CodeGen/TailDuplicator.cpp
> llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
> llvm/trunk/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
> llvm/trunk/lib/Target/AArch64/AArch64SelectionDAGInfo.h
> llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
> llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h
> llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
> llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.h
> llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
> llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
> llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
> llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
> llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
> llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h
> llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
> llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h
> llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
> llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h
> llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.h
> llvm/trunk/lib/Target/AVR/AVRISelLowering.h
> llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
> llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
> llvm/trunk/lib/Target/BPF/BPFISelLowering.cpp
> llvm/trunk/lib/Target/BPF/BPFISelLowering.h
> llvm/trunk/lib/Target/BPF/BPFInstrInfo.cpp
> llvm/trunk/lib/Target/BPF/BPFInstrInfo.h
> llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
> llvm/trunk/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonSelectionDAGInfo.h
> llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
> llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h
> llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp
> llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h
> llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
> llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.h
> llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
> llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h
> llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
> llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
> llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.h
> llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
> llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h
> llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsISelLowering.h
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
> llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
> llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
> llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h
> llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
> llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h
> llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h
> llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
> llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h
> llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp
> llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h
> llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
> llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
> llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
> llvm/trunk/lib/Target/Sparc/SparcISelLowering.h
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
> llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h
> llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
> llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
> llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.h
> llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp
> llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
> llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h
> llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
> llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h
> llvm/trunk/lib/Target/X86/X86FastISel.cpp
> llvm/trunk/lib/Target/X86/X86FrameLowering.cpp
> llvm/trunk/lib/Target/X86/X86FrameLowering.h
> llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.h
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
> llvm/trunk/lib/Target/X86/X86InstrInfo.h
> llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp
> llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.h
> llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp
> llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp
> llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
> llvm/trunk/lib/Target/XCore/XCoreISelLowering.h
> llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp
> llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h
> llvm/trunk/lib/Target/XCore/XCoreSelectionDAGInfo.cpp
> llvm/trunk/lib/Target/XCore/XCoreSelectionDAGInfo.h
> llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
> llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=272512&r1=272511&r2=272512&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Sun Jun 12 10:39:02 2016
> @@ -452,7 +452,7 @@ protected:
>
> /// \brief Emit an unconditional branch to the given block, unless it
> is the
> /// immediate (fall-through) successor, and update the CFG.
> - void fastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
> + void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL);
>
> /// Emit an unconditional branch to \p FalseMBB, obtains the branch
> weight
> /// and adds TrueMBB and FalseMBB to the successor list.
>
> Modified: llvm/trunk/include/llvm/CodeGen/GCMetadata.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GCMetadata.h?rev=272512&r1=272511&r2=272512&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/GCMetadata.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/GCMetadata.h Sun Jun 12 10:39:02 2016
> @@ -121,7 +121,7 @@ public:
> /// addSafePoint - Notes the existence of a safe point. Num is the ID
> of the
> /// label just prior to the safe point (if the code generator is using
> /// MachineModuleInfo).
> - void addSafePoint(GC::PointKind Kind, MCSymbol *Label, DebugLoc DL) {
> + void addSafePoint(GC::PointKind Kind, MCSymbol *Label, const DebugLoc
> &DL) {
> SafePoints.emplace_back(Kind, Label, DL);
> }
>
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=272512&r1=272511&r2=272512&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Sun Jun 12 10:39:02
> 2016
> @@ -502,8 +502,7 @@ public:
> /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead
> /// of `new MachineInstr'.
> ///
> - MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID,
> - DebugLoc DL,
> + MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, const
> DebugLoc &DL,
> bool NoImp = false);
>
> /// CloneMachineInstr - Create a new MachineInstr which is a copy of the
>
> Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=272512&r1=272511&r2=272512&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Sun Jun 12
> 10:39:02 2016
> @@ -237,18 +237,15 @@ public:
> };
>
> /// Builder interface. Specify how to create the initial instruction
> itself.
> -inline MachineInstrBuilder BuildMI(MachineFunction &MF,
> - DebugLoc DL,
> +inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc
> &DL,
> const MCInstrDesc &MCID) {
> return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
> }
>
> /// This version of the builder sets up the first operand as a
> /// destination virtual register.
> -inline MachineInstrBuilder BuildMI(MachineFunction &MF,
> - DebugLoc DL,
> - const MCInstrDesc &MCID,
> - unsigned DestReg) {
> +inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc
> &DL,
> + const MCInstrDesc &MCID, unsigned
> DestReg) {
> return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
> .addReg(DestReg, RegState::Define);
> }
> @@ -258,8 +255,7 @@ inline MachineInstrBuilder BuildMI(Machi
> /// operand as a destination virtual register.
> inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> MachineBasicBlock::iterator I,
> - DebugLoc DL,
> - const MCInstrDesc &MCID,
> + const DebugLoc &DL, const MCInstrDesc
> &MCID,
> unsigned DestReg) {
> MachineFunction &MF = *BB.getParent();
> MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
> @@ -269,8 +265,7 @@ inline MachineInstrBuilder BuildMI(Machi
>
> inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> MachineBasicBlock::instr_iterator I,
> - DebugLoc DL,
> - const MCInstrDesc &MCID,
> + const DebugLoc &DL, const MCInstrDesc
> &MCID,
> unsigned DestReg) {
> MachineFunction &MF = *BB.getParent();
> MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
> @@ -278,10 +273,8 @@ inline MachineInstrBuilder BuildMI(Machi
> return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
> }
>
> -inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> - MachineInstr *I,
> - DebugLoc DL,
> - const MCInstrDesc &MCID,
> +inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
> + const DebugLoc &DL, const MCInstrDesc
> &MCID,
> unsigned DestReg) {
> if (I->isInsideBundle()) {
> MachineBasicBlock::instr_iterator MII(I);
> @@ -297,7 +290,7 @@ inline MachineInstrBuilder BuildMI(Machi
> /// destination register.
> inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> MachineBasicBlock::iterator I,
> - DebugLoc DL,
> + const DebugLoc &DL,
> const MCInstrDesc &MCID) {
> MachineFunction &MF = *BB.getParent();
> MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
> @@ -307,7 +300,7 @@ inline MachineInstrBuilder BuildMI(Machi
>
> inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> MachineBasicBlock::instr_iterator I,
> - DebugLoc DL,
> + const DebugLoc &DL,
> const MCInstrDesc &MCID) {
> MachineFunction &MF = *BB.getParent();
> MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
> @@ -315,9 +308,8 @@ inline MachineInstrBuilder BuildMI(Machi
> return MachineInstrBuilder(MF, MI);
> }
>
> -inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> - MachineInstr *I,
> - DebugLoc DL,
> +inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
> + const DebugLoc &DL,
> const MCInstrDesc &MCID) {
> if (I->isInsideBundle()) {
> MachineBasicBlock::instr_iterator MII(I);
> @@ -330,8 +322,7 @@ inline MachineInstrBuilder BuildMI(Machi
>
> /// This version of the builder inserts the newly-built instruction at
> the end
> /// of the given MachineBasicBlock, and does NOT take a destination
> register.
> -inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
> - DebugLoc DL,
> +inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc
> &DL,
> const MCInstrDesc &MCID) {
> return BuildMI(*BB, BB->end(), DL, MCID);
> }
> @@ -339,10 +330,8 @@ inline MachineInstrBuilder BuildMI(Machi
> /// This version of the builder inserts the newly-built instruction at the
> /// end of the given MachineBasicBlock, and sets up the first operand as a
> /// destination virtual register.
> -inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
> - DebugLoc DL,
> - const MCInstrDesc &MCID,
> - unsigned DestReg) {
> +inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc
> &DL,
> + const MCInstrDesc &MCID, unsigned
> DestReg) {
> return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
> }
>
> @@ -350,7 +339,7 @@ inline MachineInstrBuilder BuildMI(Machi
> /// for either a value in a register or a register-indirect+offset
> /// address. The convention is that a DBG_VALUE is indirect iff the
> /// second operand is an immediate.
> -MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL,
> +MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
> const MCInstrDesc &MCID, bool IsIndirect,
> unsigned Reg, unsigned Offset,
> const MDNode *Variable, const MDNode *Expr);
> @@ -359,7 +348,7 @@ MachineInstrBuilder BuildMI(MachineFunct
> /// for either a value in a register or a register-indirect+offset
> /// address and inserts it at position I.
> MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
> - MachineBasicBlock::iterator I, DebugLoc DL,
> + MachineBasicBlock::iterator I, const DebugLoc
> &DL,
> const MCInstrDesc &MCID, bool IsIndirect,
> unsigned Reg, unsigned Offset,
> const MDNode *Variable, const MDNode *Expr);
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=272512&r1=272511&r2=272512&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Sun Jun 12 10:39:02 2016
> @@ -474,22 +474,23 @@ public:
> /// If only legal types can be produced, this does the necessary
> /// transformations (e.g., if the vector element type is illegal).
> /// @{
> - SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget =
> false,
> - bool isOpaque = false);
> - SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget =
> false,
> - bool isOpaque = false);
> - SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
> + SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
> bool isTarget = false, bool isOpaque = false);
> - SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget =
> false);
> - SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT,
> + SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
> + bool isTarget = false, bool isOpaque = false);
> + SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
> + bool isTarget = false, bool isOpaque = false);
> + SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
> + bool isTarget = false);
> + SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT,
> bool isOpaque = false) {
> return getConstant(Val, DL, VT, true, isOpaque);
> }
> - SDValue getTargetConstant(const APInt &Val, SDLoc DL, EVT VT,
> + SDValue getTargetConstant(const APInt &Val, const SDLoc &DL, EVT VT,
> bool isOpaque = false) {
> return getConstant(Val, DL, VT, true, isOpaque);
> }
> - SDValue getTargetConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
> + SDValue getTargetConstant(const ConstantInt &Val, const SDLoc &DL, EVT
> VT,
> bool isOpaque = false) {
> return getConstant(Val, DL, VT, true, isOpaque);
> }
> @@ -503,26 +504,27 @@ public:
> /// The forms that take a double should only be used for simple
> constants
> /// that can be exactly represented in VT. No checks are made.
> /// @{
> - SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget =
> false);
> - SDValue getConstantFP(const APFloat& Val, SDLoc DL, EVT VT,
> + SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT,
> + bool isTarget = false);
> + SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,
> bool isTarget = false);
> - SDValue getConstantFP(const ConstantFP &CF, SDLoc DL, EVT VT,
> + SDValue getConstantFP(const ConstantFP &CF, const SDLoc &DL, EVT VT,
> bool isTarget = false);
> - SDValue getTargetConstantFP(double Val, SDLoc DL, EVT VT) {
> + SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {
> return getConstantFP(Val, DL, VT, true);
> }
> - SDValue getTargetConstantFP(const APFloat& Val, SDLoc DL, EVT VT) {
> + SDValue getTargetConstantFP(const APFloat &Val, const SDLoc &DL, EVT
> VT) {
> return getConstantFP(Val, DL, VT, true);
> }
> - SDValue getTargetConstantFP(const ConstantFP &Val, SDLoc DL, EVT VT) {
> + SDValue getTargetConstantFP(const ConstantFP &Val, const SDLoc &DL, EVT
> VT) {
> return getConstantFP(Val, DL, VT, true);
> }
> /// @}
>
> - SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,
> + SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,
> int64_t offset = 0, bool isTargetGA = false,
> unsigned char TargetFlags = 0);
> - SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,
> + SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL,
> EVT VT,
> int64_t offset = 0,
> unsigned char TargetFlags = 0) {
> return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);
> @@ -559,7 +561,7 @@ public:
> SDValue getBasicBlock(MachineBasicBlock *MBB);
> SDValue getBasicBlock(MachineBasicBlock *MBB, SDLoc dl);
> SDValue getExternalSymbol(const char *Sym, EVT VT);
> - SDValue getExternalSymbol(const char *Sym, SDLoc dl, EVT VT);
> + SDValue getExternalSymbol(const char *Sym, const SDLoc &dl, EVT VT);
> SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
> unsigned char TargetFlags = 0);
> SDValue getMCSymbol(MCSymbol *Sym, EVT VT);
> @@ -567,7 +569,7 @@ public:
> SDValue getValueType(EVT);
> SDValue getRegister(unsigned Reg, EVT VT);
> SDValue getRegisterMask(const uint32_t *RegMask);
> - SDValue getEHLabel(SDLoc dl, SDValue Root, MCSymbol *Label);
> + SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label);
> SDValue getBlockAddress(const BlockAddress *BA, EVT VT,
> int64_t Offset = 0, bool isTarget = false,
> unsigned char TargetFlags = 0);
> @@ -577,7 +579,8 @@ public:
> return getBlockAddress(BA, VT, Offset, true, TargetFlags);
> }
>
> - SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) {
> + SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
> + SDValue N) {
> return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
> getRegister(Reg, N.getValueType()), N);
> }
> @@ -585,7 +588,7 @@ public:
> // This version of the getCopyToReg method takes an extra operand, which
> // indicates that there is potentially an incoming glue value (if Glue
> is not
> // null) and that there should be a glue result.
> - SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N,
> + SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
> SDValue N,
> SDValue Glue) {
> SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
> SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue
> };
> @@ -594,15 +597,15 @@ public:
> }
>
> // Similar to last getCopyToReg() except parameter Reg is a SDValue
> - SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N,
> - SDValue Glue) {
> + SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, SDValue Reg,
> SDValue N,
> + SDValue Glue) {
> SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
> SDValue Ops[] = { Chain, Reg, N, Glue };
> return getNode(ISD::CopyToReg, dl, VTs,
> makeArrayRef(Ops, Glue.getNode() ? 4 : 3));
> }
>
> - SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) {
> + SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
> EVT VT) {
> SDVTList VTs = getVTList(VT, MVT::Other);
> SDValue Ops[] = { Chain, getRegister(Reg, VT) };
> return getNode(ISD::CopyFromReg, dl, VTs, Ops);
> @@ -611,8 +614,8 @@ public:
> // This version of the getCopyFromReg method takes an extra operand,
> which
> // indicates that there is potentially an incoming glue value (if Glue
> is not
> // null) and that there should be a glue result.
> - SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT,
> - SDValue Glue) {
> + SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
> EVT VT,
> + SDValue Glue) {
> SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
> SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
> return getNode(ISD::CopyFromReg, dl, VTs,
> @@ -623,16 +626,16 @@ public:
>
> /// Returns the ConvertRndSat Note: Avoid using this node because it may
> /// disappear in the future and most targets don't support it.
> - SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy,
> - SDValue STy,
> - SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
> + SDValue getConvertRndSat(EVT VT, const SDLoc &dl, SDValue Val, SDValue
> DTy,
> + SDValue STy, SDValue Rnd, SDValue Sat,
> + ISD::CvtCode Code);
>
> /// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,
> /// which must be a vector type, must match the number of mask elements
> /// NumElts. An integer mask element equal to -1 is treated as
> undefined.
> - SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
> + SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue
> N2,
> const int *MaskElts);
> - SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
> + SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue
> N2,
> ArrayRef<int> MaskElts) {
> assert(VT.getVectorNumElements() == MaskElts.size() &&
> "Must have the same number of vector elements as mask
> elements!");
> @@ -643,7 +646,7 @@ public:
> /// which must be a vector type, must match the number of operands in
> Ops.
> /// The operands must have the same type as (or, for integers, a type
> wider
> /// than) VT's element type.
> - SDValue getBuildVector(EVT VT, SDLoc DL, ArrayRef<SDValue> Ops) {
> + SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDValue> Ops) {
> // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
> return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
> }
> @@ -651,7 +654,7 @@ public:
> /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to
> all
> /// elements. VT must be a vector type. Op's type must be the same as
> (or,
> /// for integers, a type wider than) VT's element type.
> - SDValue getSplatBuildVector(EVT VT, SDLoc DL, SDValue Op) {
> + SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {
> // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
> if (Op.getOpcode() == ISD::UNDEF) {
> assert((VT.getVectorElementType() == Op.getValueType() ||
> @@ -679,52 +682,52 @@ public:
>
> /// Convert Op, which must be of integer type, to the
> /// integer type VT, by either any-extending or truncating it.
> - SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
> + SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
>
> /// Convert Op, which must be of integer type, to the
> /// integer type VT, by either sign-extending or truncating it.
> - SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
> + SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
>
> /// Convert Op, which must be of integer type, to the
> /// integer type VT, by either zero-extending or truncating it.
> - SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
> + SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
>
> /// Return the expression required to zero extend the Op
> /// value assuming it was the smaller SrcTy value.
> - SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy);
> + SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy);
>
> /// Return an operation which will any-extend the low lanes of the
> operand
> /// into the specified vector type. For example,
> /// this can convert a v16i8 into a v4i32 by any-extending the low four
> /// lanes of the operand from i8 to i32.
> - SDValue getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
> + SDValue getAnyExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
>
> /// Return an operation which will sign extend the low lanes of the
> operand
> /// into the specified vector type. For example,
> /// this can convert a v16i8 into a v4i32 by sign extending the low four
> /// lanes of the operand from i8 to i32.
> - SDValue getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
> + SDValue getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
>
> /// Return an operation which will zero extend the low lanes of the
> operand
> /// into the specified vector type. For example,
> /// this can convert a v16i8 into a v4i32 by zero extending the low four
> /// lanes of the operand from i8 to i32.
> - SDValue getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);
> + SDValue getZeroExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
>
> /// Convert Op, which must be of integer type, to the integer type VT,
> /// by using an extension appropriate for the target's
> /// BooleanContent for type OpVT or truncating it.
> - SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT);
> + SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT
> OpVT);
>
> /// Create a bitwise NOT operation as (XOR Val, -1).
> - SDValue getNOT(SDLoc DL, SDValue Val, EVT VT);
> + SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);
>
> /// \brief Create a logical NOT operation as (XOR Val, BooleanOne).
> - SDValue getLogicalNOT(SDLoc DL, SDValue Val, EVT VT);
> + SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);
>
> /// Return a new CALLSEQ_START node, which always must have a glue
> result
> /// (to ensure it's not CSE'd). CALLSEQ_START does not have a useful
> SDLoc.
> - SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL) {
> + SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL) {
> SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
> SDValue Ops[] = { Chain, Op };
> return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
> @@ -734,7 +737,7 @@ public:
> /// glue result (to ensure it's not CSE'd).
> /// CALLSEQ_END does not have a useful SDLoc.
> SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
> - SDValue InGlue, SDLoc DL) {
> + SDValue InGlue, const SDLoc &DL) {
> SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue);
> SmallVector<SDValue, 4> Ops;
> Ops.push_back(Chain);
> @@ -757,38 +760,38 @@ public:
>
> /// Gets or creates the specified node.
> ///
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
> ArrayRef<SDUse> Ops);
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
> ArrayRef<SDValue> Ops, const SDNodeFlags *Flags =
> nullptr);
> - SDValue getNode(unsigned Opcode, SDLoc DL, ArrayRef<EVT> ResultTys,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT>
> ResultTys,
> ArrayRef<SDValue> Ops);
> - SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
> ArrayRef<SDValue> Ops);
>
> // Specialize based on number of operands.
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue
> N2,
> - const SDNodeFlags *Flags = nullptr);
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue
> N2,
> - SDValue N3);
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue
> N2,
> - SDValue N3, SDValue N4);
> - SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue
> N2,
> - SDValue N3, SDValue N4, SDValue N5);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
> + SDValue N2, const SDNodeFlags *Flags = nullptr);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
> + SDValue N2, SDValue N3);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
> + SDValue N2, SDValue N3, SDValue N4);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
> + SDValue N2, SDValue N3, SDValue N4, SDValue N5);
>
> // Specialize again based on number of operands for nodes with a VTList
> // rather than a single VT.
> - SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);
> - SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N);
> - SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue
> N);
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue
> N1,
> SDValue N2);
> - SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue
> N1,
> SDValue N2, SDValue N3);
> - SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue
> N1,
> SDValue N2, SDValue N3, SDValue N4);
> - SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,
> + SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue
> N1,
> SDValue N2, SDValue N3, SDValue N4, SDValue N5);
>
> /// Compute a TokenFactor to force all the incoming stack arguments to
> be
> @@ -796,24 +799,24 @@ public:
> /// stack arguments from being clobbered.
> SDValue getStackArgumentTokenFactor(SDValue Chain);
>
> - SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
> + SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue
> Src,
> SDValue Size, unsigned Align, bool isVol, bool
> AlwaysInline,
> bool isTailCall, MachinePointerInfo DstPtrInfo,
> MachinePointerInfo SrcPtrInfo);
>
> - SDValue getMemmove(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
> + SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue
> Src,
> SDValue Size, unsigned Align, bool isVol, bool
> isTailCall,
> MachinePointerInfo DstPtrInfo,
> MachinePointerInfo SrcPtrInfo);
>
> - SDValue getMemset(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
> + SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue
> Src,
> SDValue Size, unsigned Align, bool isVol, bool
> isTailCall,
> MachinePointerInfo DstPtrInfo);
>
> /// Helper function to make it easier to build SetCC's if you just
> /// have an ISD::CondCode instead of an SDValue.
> ///
> - SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
> + SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,
> ISD::CondCode Cond) {
> assert(LHS.getValueType().isVector() == RHS.getValueType().isVector()
> &&
> "Cannot compare scalars to vectors");
> @@ -826,8 +829,8 @@ public:
>
> /// Helper function to make it easier to build Select's if you just
> /// have operands and don't want to check for vector.
> - SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond,
> - SDValue LHS, SDValue RHS) {
> + SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS,
> + SDValue RHS) {
> assert(LHS.getValueType() == RHS.getValueType() &&
> "Cannot use select on differing types");
> assert(VT.isVector() == LHS.getValueType().isVector() &&
> @@ -839,142 +842,137 @@ public:
> /// Helper function to make it easier to build SelectCC's if you
> /// just have an ISD::CondCode instead of an SDValue.
> ///
> - SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS,
> - SDValue True, SDValue False, ISD::CondCode Cond) {
> + SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue
> True,
> + SDValue False, ISD::CondCode Cond) {
> return getNode(ISD::SELECT_CC, DL, True.getValueType(),
> LHS, RHS, True, False, getCondCode(Cond));
> }
>
> /// VAArg produces a result and token chain, and takes a pointer
> /// and a source value as input.
> - SDValue getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
> + SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
> SDValue SV, unsigned Align);
>
> /// Gets a node for an atomic cmpxchg op. There are two
> /// valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a
> /// chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value
> loaded,
> /// a success flag (initially i1), and a chain.
> - SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList
> VTs,
> - SDValue Chain, SDValue Ptr, SDValue Cmp,
> SDValue Swp,
> - MachinePointerInfo PtrInfo, unsigned Alignment,
> - AtomicOrdering SuccessOrdering,
> + SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
> + SDVTList VTs, SDValue Chain, SDValue Ptr,
> + SDValue Cmp, SDValue Swp, MachinePointerInfo
> PtrInfo,
> + unsigned Alignment, AtomicOrdering
> SuccessOrdering,
> AtomicOrdering FailureOrdering,
> SynchronizationScope SynchScope);
> - SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList
> VTs,
> - SDValue Chain, SDValue Ptr, SDValue Cmp,
> SDValue Swp,
> - MachineMemOperand *MMO,
> + SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
> + SDVTList VTs, SDValue Chain, SDValue Ptr,
> + SDValue Cmp, SDValue Swp, MachineMemOperand
> *MMO,
> AtomicOrdering SuccessOrdering,
> AtomicOrdering FailureOrdering,
> SynchronizationScope SynchScope);
>
> /// Gets a node for an atomic op, produces result (if relevant)
> /// and chain and takes 2 operands.
> - SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
> + SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue
> Chain,
> SDValue Ptr, SDValue Val, const Value *PtrVal,
> unsigned Alignment, AtomicOrdering Ordering,
> SynchronizationScope SynchScope);
> - SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
> + SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue
> Chain,
> SDValue Ptr, SDValue Val, MachineMemOperand *MMO,
> - AtomicOrdering Ordering,
> - SynchronizationScope SynchScope);
> + AtomicOrdering Ordering, SynchronizationScope
> SynchScope);
>
> /// Gets a node for an atomic op, produces result and chain and
> /// takes 1 operand.
> - SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT,
> + SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT,
> SDValue Chain, SDValue Ptr, MachineMemOperand *MMO,
> - AtomicOrdering Ordering,
> - SynchronizationScope SynchScope);
> + AtomicOrdering Ordering, SynchronizationScope
> SynchScope);
>
> /// Gets a node for an atomic op, produces result and chain and takes N
> /// operands.
> - SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,
> - ArrayRef<SDValue> Ops, MachineMemOperand *MMO,
> - AtomicOrdering SuccessOrdering,
> + SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
> + SDVTList VTList, ArrayRef<SDValue> Ops,
> + MachineMemOperand *MMO, AtomicOrdering
> SuccessOrdering,
> AtomicOrdering FailureOrdering,
> SynchronizationScope SynchScope);
> - SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,
> - ArrayRef<SDValue> Ops, MachineMemOperand *MMO,
> - AtomicOrdering Ordering, SynchronizationScope
> SynchScope);
> + SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
> + SDVTList VTList, ArrayRef<SDValue> Ops,
> + MachineMemOperand *MMO, AtomicOrdering Ordering,
> + SynchronizationScope SynchScope);
>
> /// Creates a MemIntrinsicNode that may produce a
> /// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
> /// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
> /// less than FIRST_TARGET_MEMORY_OPCODE.
> - SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
> - ArrayRef<SDValue> Ops,
> - EVT MemVT, MachinePointerInfo PtrInfo,
> - unsigned Align = 0, bool Vol = false,
> - bool ReadMem = true, bool WriteMem = true,
> - unsigned Size = 0);
> -
> - SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
> - ArrayRef<SDValue> Ops,
> - EVT MemVT, MachineMemOperand *MMO);
> + SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList
> VTList,
> + ArrayRef<SDValue> Ops, EVT MemVT,
> + MachinePointerInfo PtrInfo, unsigned Align
> = 0,
> + bool Vol = false, bool ReadMem = true,
> + bool WriteMem = true, unsigned Size = 0);
> +
> + SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList
> VTList,
> + ArrayRef<SDValue> Ops, EVT MemVT,
> + MachineMemOperand *MMO);
>
> /// Create a MERGE_VALUES node from the given operands.
> - SDValue getMergeValues(ArrayRef<SDValue> Ops, SDLoc dl);
> + SDValue getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl);
>
> /// Loads are not normal binary operators: their result type is not
> /// determined by their operands, and they produce a value AND a token
> chain.
> ///
> - SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
> + SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
> MachinePointerInfo PtrInfo, bool isVolatile,
> bool isNonTemporal, bool isInvariant, unsigned
> Alignment,
> const AAMDNodes &AAInfo = AAMDNodes(),
> const MDNode *Ranges = nullptr);
> - SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
> + SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
> MachineMemOperand *MMO);
> - SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
> + SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
> SDValue Chain, SDValue Ptr, MachinePointerInfo
> PtrInfo,
> - EVT MemVT, bool isVolatile,
> - bool isNonTemporal, bool isInvariant, unsigned
> Alignment,
> + EVT MemVT, bool isVolatile, bool isNonTemporal,
> + bool isInvariant, unsigned Alignment,
> const AAMDNodes &AAInfo = AAMDNodes());
> - SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
> + SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
> SDValue Chain, SDValue Ptr, EVT MemVT,
> MachineMemOperand *MMO);
> - SDValue getIndexedLoad(SDValue OrigLoad, SDLoc dl, SDValue Base,
> + SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base,
> SDValue Offset, ISD::MemIndexedMode AM);
> - SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
> - EVT VT, SDLoc dl,
> - SDValue Chain, SDValue Ptr, SDValue Offset,
> - MachinePointerInfo PtrInfo, EVT MemVT,
> - bool isVolatile, bool isNonTemporal, bool isInvariant,
> - unsigned Alignment, const AAMDNodes &AAInfo =
> AAMDNodes(),
> + SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT
> VT,
> + const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue
> Offset,
> + MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile,
> + bool isNonTemporal, bool isInvariant, unsigned
> Alignment,
> + const AAMDNodes &AAInfo = AAMDNodes(),
> const MDNode *Ranges = nullptr);
> - SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
> - EVT VT, SDLoc dl,
> - SDValue Chain, SDValue Ptr, SDValue Offset,
> + SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT
> VT,
> + const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue
> Offset,
> EVT MemVT, MachineMemOperand *MMO);
>
> /// Helper function to build ISD::STORE nodes.
> - SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
> + SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue
> Ptr,
> MachinePointerInfo PtrInfo, bool isVolatile,
> bool isNonTemporal, unsigned Alignment,
> const AAMDNodes &AAInfo = AAMDNodes());
> - SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
> + SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue
> Ptr,
> MachineMemOperand *MMO);
> - SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
> - MachinePointerInfo PtrInfo, EVT TVT,
> - bool isNonTemporal, bool isVolatile,
> - unsigned Alignment,
> + SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
> + SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT,
> + bool isNonTemporal, bool isVolatile, unsigned
> Alignment,
> const AAMDNodes &AAInfo = AAMDNodes());
> - SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
> - EVT TVT, MachineMemOperand *MMO);
> - SDValue getIndexedStore(SDValue OrigStoe, SDLoc dl, SDValue Base,
> + SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
> + SDValue Ptr, EVT TVT, MachineMemOperand *MMO);
> + SDValue getIndexedStore(SDValue OrigStoe, const SDLoc &dl, SDValue Base,
> SDValue Offset, ISD::MemIndexedMode AM);
>
> /// Returns sum of the base pointer and offset.
> - SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc DL);
> + SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc
> &DL);
>
> - SDValue getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
> + SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue
> Ptr,
> SDValue Mask, SDValue Src0, EVT MemVT,
> MachineMemOperand *MMO, ISD::LoadExtType);
> - SDValue getMaskedStore(SDValue Chain, SDLoc dl, SDValue Val,
> + SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val,
> SDValue Ptr, SDValue Mask, EVT MemVT,
> MachineMemOperand *MMO, bool IsTrunc);
> - SDValue getMaskedGather(SDVTList VTs, EVT VT, SDLoc dl,
> + SDValue getMaskedGather(SDVTList VTs, EVT VT, const SDLoc &dl,
> ArrayRef<SDValue> Ops, MachineMemOperand *MMO);
> - SDValue getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl,
> + SDValue getMaskedScatter(SDVTList VTs, EVT VT, const SDLoc &dl,
> ArrayRef<SDValue> Ops, MachineMemOperand *MMO);
> /// Construct a node to track a Value* through the backend.
> SDValue getSrcValue(const Value *v);
> @@ -987,8 +985,8 @@ public:
> SDValue getBitcast(EVT VT, SDValue V);
>
> /// Return an AddrSpaceCastSDNode.
> - SDValue getAddrSpaceCast(SDLoc dl, EVT VT, SDValue Ptr,
> - unsigned SrcAS, unsigned DestAS);
> + SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned
> SrcAS,
> + unsigned DestAS);
>
> /// Return the specified value casted to
> /// the target's desired shift amount type.
> @@ -1057,45 +1055,46 @@ public:
> /// Note that getMachineNode returns the resultant node. If there is
> already
> /// a node of the specified opcode and operands, it returns that node
> instead
> /// of the current one.
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
> SDValue Op1);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
> SDValue Op1, SDValue Op2);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
> SDValue Op1, SDValue Op2, SDValue Op3);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
> ArrayRef<SDValue> Ops);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - SDValue Op1);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - SDValue Op1, SDValue Op2);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - SDValue Op1, SDValue Op2, SDValue Op3);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - ArrayRef<SDValue> Ops);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - EVT VT3, SDValue Op1, SDValue Op2);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - EVT VT3, SDValue Op1, SDValue Op2,
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, SDValue Op1);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, SDValue Op1, SDValue Op2);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, SDValue Op1, SDValue Op2,
> SDValue Op3);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, ArrayRef<SDValue> Ops);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, EVT VT3, SDValue Op1, SDValue
> Op2);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, EVT VT3, SDValue Op1, SDValue
> Op2,
> SDValue Op3);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - EVT VT3, ArrayRef<SDValue> Ops);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT
> VT2,
> - EVT VT3, EVT VT4, ArrayRef<SDValue> Ops);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl,
> - ArrayRef<EVT> ResultTys,
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
> + EVT VT2, EVT VT3, EVT VT4,
> ArrayRef<SDValue> Ops);
> - MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, SDVTList VTs,
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl,
> + ArrayRef<EVT> ResultTys,
> ArrayRef<SDValue> Ops);
> + MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl,
> SDVTList VTs,
> ArrayRef<SDValue> Ops);
>
> /// A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG
> nodes.
> - SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT,
> + SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
> SDValue Operand);
>
> /// A convenience function for creating TargetInstrInfo::INSERT_SUBREG
> nodes.
> - SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,
> + SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
> SDValue Operand, SDValue Subreg);
>
> /// Get the specified node if it's already available, or else return
> NULL.
> @@ -1104,16 +1103,17 @@ public:
>
> /// Creates a SDDbgValue node.
> SDDbgValue *getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N, unsigned
> R,
> - bool IsIndirect, uint64_t Off, DebugLoc DL,
> + bool IsIndirect, uint64_t Off, const DebugLoc
> &DL,
> unsigned O);
>
> /// Constant
> SDDbgValue *getConstantDbgValue(MDNode *Var, MDNode *Expr, const Value
> *C,
> - uint64_t Off, DebugLoc DL, unsigned O);
> + uint64_t Off, const DebugLoc &DL,
> unsigned O);
>
> /// FrameIndex
> SDDbgValue *getFrameIndexDbgValue(MDNode *Var, MDNode *Expr, unsigned
> FI,
> - uint64_t Off, DebugLoc DL, unsigned
> O);
> + uint64_t Off, const DebugLoc &DL,
> + unsigned O);
>
> /// Remove the specified node from the system. If any of its
> /// operands then becomes dead, remove them as well. Inform
> UpdateListener
> @@ -1252,20 +1252,20 @@ public:
> const GlobalAddressSDNode *GA,
> const SDNode *N2);
>
> - SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
> + SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
> SDNode *Cst1, SDNode *Cst2);
>
> - SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,
> + SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
> const ConstantSDNode *Cst1,
> const ConstantSDNode *Cst2);
>
> - SDValue FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL,
> - EVT VT, ArrayRef<SDValue> Ops,
> + SDValue FoldConstantVectorArithmetic(unsigned Opcode, const SDLoc &DL,
> EVT VT,
> + ArrayRef<SDValue> Ops,
> const SDNodeFlags *Flags =
> nullptr);
>
> /// Constant fold a setcc to true or false.
> - SDValue FoldSetCC(EVT VT, SDValue N1,
> - SDValue N2, ISD::CondCode Cond, SDLoc dl);
> + SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond,
> + const SDLoc &dl);
>
> /// Return true if the sign bit of Op is known to be zero.
> /// We use this predicate to simplify operations downstream.
> @@ -1389,8 +1389,9 @@ private:
>
> void allnodes_clear();
>
> - SDNode *GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
> SDValue N1,
> - SDValue N2, const SDNodeFlags *Flags = nullptr);
> + SDNode *GetBinarySDNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
> + SDValue N1, SDValue N2,
> + const SDNodeFlags *Flags = nullptr);
>
> /// Look up the node specified by ID in CSEMap. If it exists, return
> it. If
> /// not, return the insertion token that will make insertion faster.
> This
> @@ -1401,7 +1402,7 @@ private:
> /// Look up the node specified by ID in CSEMap. If it exists, return
> it. If
> /// not, return the insertion token that will make insertion faster.
> Performs
> /// additional processing for constant nodes.
> - SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, SDLoc DL,
> + SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, const SDLoc &DL,
> void *&InsertPos);
>
> /// List of non-single value types.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=272512&r1=272511&r2=272512&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Sun Jun 12 10:39:02
> 2016
> @@ -210,8 +210,8 @@ protected:
>
> /// SelectInlineAsmMemoryOperands - Calls to this are automatically
> generated
> /// by tblgen. Others should not call it.
> - void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL);
> -
> + void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
> + const SDLoc &DL);
>
> public:
> // Calls to these predicates are generated by tblgen.
>
> Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=272512&r1=272511&r2=272512&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Sun Jun 12
> 10:39:02 2016
> @@ -847,8 +847,8 @@ public:
> if (I)
> DL = I->getDebugLoc();
> }
> - unsigned getIROrder() { return IROrder; }
> - DebugLoc getDebugLoc() { return DL; }
> + unsigned getIROrder() const { return IROrder; }
> + const DebugLoc &getDebugLoc() const { return DL; }
> };
>
>
> @@ -952,8 +952,8 @@ static bool isBinOpWithFlags(unsigned Op
> class BinaryWithFlagsSDNode : public SDNode {
> public:
> SDNodeFlags Flags;
> - BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl,
> SDVTList VTs,
> - const SDNodeFlags &NodeFlags)
> + BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
> + SDVTList VTs, const SDNodeFlags &NodeFlags)
> : SDNode(Opc, Order, dl, VTs), Flags(NodeFlags) {}
> static bool classof(const SDNode *N) {
> return isBinOpWithFlags(N->getOpcode());
> @@ -992,8 +992,8 @@ private:
> unsigned DestAddrSpace;
>
> public:
> - AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT, unsigned SrcAS,
> - unsigned DestAS);
> + AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
> + unsigned SrcAS, unsigned DestAS);
>
> unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
> unsigned getDestAddressSpace() const { return DestAddrSpace; }
> @@ -1014,7 +1014,7 @@ protected:
> MachineMemOperand *MMO;
>
> public:
> - MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
> + MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList
> VTs,
> EVT MemoryVT, MachineMemOperand *MMO);
>
> bool readMem() const { return MMO->isLoad(); }
> @@ -1146,7 +1146,7 @@ class AtomicSDNode : public MemSDNode {
> }
>
> public:
> - AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL,
> + AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList
> VTL,
> EVT MemVT, MachineMemOperand *MMO,
> AtomicOrdering SuccessOrdering, AtomicOrdering
> FailureOrdering,
> SynchronizationScope SynchScope)
> @@ -1198,8 +1198,8 @@ public:
> /// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
> class MemIntrinsicSDNode : public MemSDNode {
> public:
> - MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList
> VTs,
> - EVT MemoryVT, MachineMemOperand *MMO)
> + MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
> + SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
> : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
> SubclassData |= 1u << 13;
> }
> @@ -1228,7 +1228,7 @@ class ShuffleVectorSDNode : public SDNod
> const int *Mask;
> protected:
> friend class SelectionDAG;
> - ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, const int *M)
> + ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const
> int *M)
> : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M)
> {}
>
> public:
> @@ -1277,9 +1277,10 @@ class ConstantSDNode : public SDNode {
> const ConstantInt *Value;
> friend class SelectionDAG;
> ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val,
> - DebugLoc DL, EVT VT)
> - : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
> - 0, DL, getSDVTList(VT)), Value(val) {
> + const DebugLoc &DL, EVT VT)
> + : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DL,
> + getSDVTList(VT)),
> + Value(val) {
> SubclassData |= (uint16_t)isOpaque;
> }
> public:
> @@ -1304,10 +1305,12 @@ public:
> class ConstantFPSDNode : public SDNode {
> const ConstantFP *Value;
> friend class SelectionDAG;
> - ConstantFPSDNode(bool isTarget, const ConstantFP *val, DebugLoc DL, EVT
> VT)
> - : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
> - 0, DL, getSDVTList(VT)), Value(val) {
> - }
> + ConstantFPSDNode(bool isTarget, const ConstantFP *val, const DebugLoc
> &DL,
> + EVT VT)
> + : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0, DL,
> + getSDVTList(VT)),
> + Value(val) {}
> +
> public:
>
> const APFloat& getValueAPF() const { return Value->getValueAPF(); }
> @@ -1367,9 +1370,10 @@ class GlobalAddressSDNode : public SDNod
> int64_t Offset;
> unsigned char TargetFlags;
> friend class SelectionDAG;
> - GlobalAddressSDNode(unsigned Opc, unsigned Order, DebugLoc DL,
> + GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
> const GlobalValue *GA, EVT VT, int64_t o,
> unsigned char TargetFlags);
> +
> public:
>
> const GlobalValue *getGlobal() const { return TheGlobal; }
> @@ -1667,7 +1671,7 @@ public:
> class EHLabelSDNode : public SDNode {
> MCSymbol *Label;
> friend class SelectionDAG;
> - EHLabelSDNode(unsigned Order, DebugLoc dl, MCSymbol *L)
> + EHLabelSDNode(unsigned Order, const DebugLoc &dl, MCSymbol *L)
> : SDNode(ISD::EH_LABEL, Order, dl, getSDVTList(MVT::Other)),
> Label(L) {}
>
> public:
> @@ -1734,7 +1738,7 @@ public:
> class CvtRndSatSDNode : public SDNode {
> ISD::CvtCode CvtCode;
> friend class SelectionDAG;
> - explicit CvtRndSatSDNode(EVT VT, unsigned Order, DebugLoc dl,
> + explicit CvtRndSatSDNode(EVT VT, unsigned Order, const DebugLoc &dl,
> ISD::CvtCode Code)
> : SDNode(ISD::CONVERT_RNDSAT, Order, dl, getSDVTList(VT)),
> CvtCode(Code) {
> }
> @@ -1768,10 +1772,10 @@ public:
> /// Base class for LoadSDNode and StoreSDNode
> class LSBaseSDNode : public MemSDNode {
> public:
> - LSBaseSDNode(ISD::
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160612/7bcc8cd2/attachment-0001.html>
More information about the llvm-commits
mailing list