<p dir="ltr">Hey, awesome. Thanks!</p>
<br><div class="gmail_quote"><div dir="ltr">On Sun, Jun 12, 2016, 8:45 AM Benjamin Kramer via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: d0k<br>
Date: Sun Jun 12 10:39:02 2016<br>
New Revision: 272512<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=272512&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=272512&view=rev</a><br>
Log:<br>
Pass DebugLoc and SDLoc by const ref.<br>
<br>
This used to be free, copying and moving DebugLocs became expensive<br>
after the metadata rewrite. Passing by reference eliminates a ton of<br>
track/untrack operations. No functionality change intended.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
llvm/trunk/include/llvm/CodeGen/GCMetadata.h<br>
llvm/trunk/include/llvm/CodeGen/MachineFunction.h<br>
llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h<br>
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h<br>
llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h<br>
llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h<br>
llvm/trunk/include/llvm/CodeGen/SelectionDAGTargetInfo.h<br>
llvm/trunk/include/llvm/Target/TargetInstrInfo.h<br>
llvm/trunk/include/llvm/Target/TargetLowering.h<br>
llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp<br>
llvm/trunk/lib/CodeGen/AsmPrinter/CodeViewDebug.h<br>
llvm/trunk/lib/CodeGen/GCRootLowering.cpp<br>
llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp<br>
llvm/trunk/lib/CodeGen/MachineFunction.cpp<br>
llvm/trunk/lib/CodeGen/MachineInstr.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp<br>
llvm/trunk/lib/CodeGen/TailDuplicator.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h<br>
llvm/trunk/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp<br>
llvm/trunk/lib/Target/AArch64/AArch64SelectionDAGInfo.h<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.h<br>
llvm/trunk/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp<br>
llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/R600ISelLowering.h<br>
llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h<br>
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp<br>
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h<br>
llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp<br>
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h<br>
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h<br>
llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br>
llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp<br>
llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ARMSelectionDAGInfo.h<br>
llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp<br>
llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.h<br>
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp<br>
llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h<br>
llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.cpp<br>
llvm/trunk/lib/Target/ARM/ThumbRegisterInfo.h<br>
llvm/trunk/lib/Target/AVR/AVRISelLowering.h<br>
llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp<br>
llvm/trunk/lib/Target/AVR/AVRInstrInfo.h<br>
llvm/trunk/lib/Target/BPF/BPFISelLowering.cpp<br>
llvm/trunk/lib/Target/BPF/BPFISelLowering.h<br>
llvm/trunk/lib/Target/BPF/BPFInstrInfo.cpp<br>
llvm/trunk/lib/Target/BPF/BPFInstrInfo.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h<br>
llvm/trunk/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonSelectionDAGInfo.h<br>
llvm/trunk/lib/Target/Lanai/LanaiISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp<br>
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h<br>
llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp<br>
llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h<br>
llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp<br>
llvm/trunk/lib/Target/Lanai/LanaiSelectionDAGInfo.h<br>
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp<br>
llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.h<br>
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp<br>
llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h<br>
llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/Mips/Mips16ISelDAGToDAG.h<br>
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp<br>
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.h<br>
llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp<br>
llvm/trunk/lib/Target/Mips/MipsInstrInfo.h<br>
llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp<br>
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/Mips/MipsSEISelDAGToDAG.h<br>
llvm/trunk/lib/Target/Mips/MipsSEISelLowering.cpp<br>
llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp<br>
llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelDAGToDAG.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.h<br>
llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp<br>
llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h<br>
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h<br>
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp<br>
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h<br>
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcISelLowering.h<br>
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp<br>
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h<br>
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.h<br>
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h<br>
llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp<br>
llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.h<br>
llvm/trunk/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp<br>
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp<br>
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.h<br>
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp<br>
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h<br>
llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>
llvm/trunk/lib/Target/X86/X86FrameLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86FrameLowering.h<br>
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.h<br>
llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.h<br>
llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreISelLowering.h<br>
llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h<br>
llvm/trunk/lib/Target/XCore/XCoreSelectionDAGInfo.cpp<br>
llvm/trunk/lib/Target/XCore/XCoreSelectionDAGInfo.h<br>
llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp<br>
llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=272512&r1=272511&r2=272512&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=272512&r1=272511&r2=272512&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Sun Jun 12 10:39:02 2016<br>
@@ -452,7 +452,7 @@ protected:<br>
<br>
/// \brief Emit an unconditional branch to the given block, unless it is the<br>
/// immediate (fall-through) successor, and update the CFG.<br>
- void fastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);<br>
+ void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL);<br>
<br>
/// Emit an unconditional branch to \p FalseMBB, obtains the branch weight<br>
/// and adds TrueMBB and FalseMBB to the successor list.<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/GCMetadata.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GCMetadata.h?rev=272512&r1=272511&r2=272512&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GCMetadata.h?rev=272512&r1=272511&r2=272512&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/GCMetadata.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/GCMetadata.h Sun Jun 12 10:39:02 2016<br>
@@ -121,7 +121,7 @@ public:<br>
/// addSafePoint - Notes the existence of a safe point. Num is the ID of the<br>
/// label just prior to the safe point (if the code generator is using<br>
/// MachineModuleInfo).<br>
- void addSafePoint(GC::PointKind Kind, MCSymbol *Label, DebugLoc DL) {<br>
+ void addSafePoint(GC::PointKind Kind, MCSymbol *Label, const DebugLoc &DL) {<br>
SafePoints.emplace_back(Kind, Label, DL);<br>
}<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=272512&r1=272511&r2=272512&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=272512&r1=272511&r2=272512&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Sun Jun 12 10:39:02 2016<br>
@@ -502,8 +502,7 @@ public:<br>
/// CreateMachineInstr - Allocate a new MachineInstr. Use this instead<br>
/// of `new MachineInstr'.<br>
///<br>
- MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID,<br>
- DebugLoc DL,<br>
+ MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL,<br>
bool NoImp = false);<br>
<br>
/// CloneMachineInstr - Create a new MachineInstr which is a copy of the<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=272512&r1=272511&r2=272512&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=272512&r1=272511&r2=272512&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Sun Jun 12 10:39:02 2016<br>
@@ -237,18 +237,15 @@ public:<br>
};<br>
<br>
/// Builder interface. Specify how to create the initial instruction itself.<br>
-inline MachineInstrBuilder BuildMI(MachineFunction &MF,<br>
- DebugLoc DL,<br>
+inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,<br>
const MCInstrDesc &MCID) {<br>
return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));<br>
}<br>
<br>
/// This version of the builder sets up the first operand as a<br>
/// destination virtual register.<br>
-inline MachineInstrBuilder BuildMI(MachineFunction &MF,<br>
- DebugLoc DL,<br>
- const MCInstrDesc &MCID,<br>
- unsigned DestReg) {<br>
+inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,<br>
+ const MCInstrDesc &MCID, unsigned DestReg) {<br>
return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))<br>
.addReg(DestReg, RegState::Define);<br>
}<br>
@@ -258,8 +255,7 @@ inline MachineInstrBuilder BuildMI(Machi<br>
/// operand as a destination virtual register.<br>
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
MachineBasicBlock::iterator I,<br>
- DebugLoc DL,<br>
- const MCInstrDesc &MCID,<br>
+ const DebugLoc &DL, const MCInstrDesc &MCID,<br>
unsigned DestReg) {<br>
MachineFunction &MF = *BB.getParent();<br>
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);<br>
@@ -269,8 +265,7 @@ inline MachineInstrBuilder BuildMI(Machi<br>
<br>
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
MachineBasicBlock::instr_iterator I,<br>
- DebugLoc DL,<br>
- const MCInstrDesc &MCID,<br>
+ const DebugLoc &DL, const MCInstrDesc &MCID,<br>
unsigned DestReg) {<br>
MachineFunction &MF = *BB.getParent();<br>
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);<br>
@@ -278,10 +273,8 @@ inline MachineInstrBuilder BuildMI(Machi<br>
return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);<br>
}<br>
<br>
-inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
- MachineInstr *I,<br>
- DebugLoc DL,<br>
- const MCInstrDesc &MCID,<br>
+inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,<br>
+ const DebugLoc &DL, const MCInstrDesc &MCID,<br>
unsigned DestReg) {<br>
if (I->isInsideBundle()) {<br>
MachineBasicBlock::instr_iterator MII(I);<br>
@@ -297,7 +290,7 @@ inline MachineInstrBuilder BuildMI(Machi<br>
/// destination register.<br>
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
MachineBasicBlock::iterator I,<br>
- DebugLoc DL,<br>
+ const DebugLoc &DL,<br>
const MCInstrDesc &MCID) {<br>
MachineFunction &MF = *BB.getParent();<br>
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);<br>
@@ -307,7 +300,7 @@ inline MachineInstrBuilder BuildMI(Machi<br>
<br>
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
MachineBasicBlock::instr_iterator I,<br>
- DebugLoc DL,<br>
+ const DebugLoc &DL,<br>
const MCInstrDesc &MCID) {<br>
MachineFunction &MF = *BB.getParent();<br>
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);<br>
@@ -315,9 +308,8 @@ inline MachineInstrBuilder BuildMI(Machi<br>
return MachineInstrBuilder(MF, MI);<br>
}<br>
<br>
-inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
- MachineInstr *I,<br>
- DebugLoc DL,<br>
+inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,<br>
+ const DebugLoc &DL,<br>
const MCInstrDesc &MCID) {<br>
if (I->isInsideBundle()) {<br>
MachineBasicBlock::instr_iterator MII(I);<br>
@@ -330,8 +322,7 @@ inline MachineInstrBuilder BuildMI(Machi<br>
<br>
/// This version of the builder inserts the newly-built instruction at the end<br>
/// of the given MachineBasicBlock, and does NOT take a destination register.<br>
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,<br>
- DebugLoc DL,<br>
+inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,<br>
const MCInstrDesc &MCID) {<br>
return BuildMI(*BB, BB->end(), DL, MCID);<br>
}<br>
@@ -339,10 +330,8 @@ inline MachineInstrBuilder BuildMI(Machi<br>
/// This version of the builder inserts the newly-built instruction at the<br>
/// end of the given MachineBasicBlock, and sets up the first operand as a<br>
/// destination virtual register.<br>
-inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,<br>
- DebugLoc DL,<br>
- const MCInstrDesc &MCID,<br>
- unsigned DestReg) {<br>
+inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,<br>
+ const MCInstrDesc &MCID, unsigned DestReg) {<br>
return BuildMI(*BB, BB->end(), DL, MCID, DestReg);<br>
}<br>
<br>
@@ -350,7 +339,7 @@ inline MachineInstrBuilder BuildMI(Machi<br>
/// for either a value in a register or a register-indirect+offset<br>
/// address. The convention is that a DBG_VALUE is indirect iff the<br>
/// second operand is an immediate.<br>
-MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL,<br>
+MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,<br>
const MCInstrDesc &MCID, bool IsIndirect,<br>
unsigned Reg, unsigned Offset,<br>
const MDNode *Variable, const MDNode *Expr);<br>
@@ -359,7 +348,7 @@ MachineInstrBuilder BuildMI(MachineFunct<br>
/// for either a value in a register or a register-indirect+offset<br>
/// address and inserts it at position I.<br>
MachineInstrBuilder BuildMI(MachineBasicBlock &BB,<br>
- MachineBasicBlock::iterator I, DebugLoc DL,<br>
+ MachineBasicBlock::iterator I, const DebugLoc &DL,<br>
const MCInstrDesc &MCID, bool IsIndirect,<br>
unsigned Reg, unsigned Offset,<br>
const MDNode *Variable, const MDNode *Expr);<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=272512&r1=272511&r2=272512&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=272512&r1=272511&r2=272512&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Sun Jun 12 10:39:02 2016<br>
@@ -474,22 +474,23 @@ public:<br>
/// If only legal types can be produced, this does the necessary<br>
/// transformations (e.g., if the vector element type is illegal).<br>
/// @{<br>
- SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false,<br>
- bool isOpaque = false);<br>
- SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false,<br>
- bool isOpaque = false);<br>
- SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,<br>
+ SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,<br>
bool isTarget = false, bool isOpaque = false);<br>
- SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget = false);<br>
- SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT,<br>
+ SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,<br>
+ bool isTarget = false, bool isOpaque = false);<br>
+ SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,<br>
+ bool isTarget = false, bool isOpaque = false);<br>
+ SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,<br>
+ bool isTarget = false);<br>
+ SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT,<br>
bool isOpaque = false) {<br>
return getConstant(Val, DL, VT, true, isOpaque);<br>
}<br>
- SDValue getTargetConstant(const APInt &Val, SDLoc DL, EVT VT,<br>
+ SDValue getTargetConstant(const APInt &Val, const SDLoc &DL, EVT VT,<br>
bool isOpaque = false) {<br>
return getConstant(Val, DL, VT, true, isOpaque);<br>
}<br>
- SDValue getTargetConstant(const ConstantInt &Val, SDLoc DL, EVT VT,<br>
+ SDValue getTargetConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,<br>
bool isOpaque = false) {<br>
return getConstant(Val, DL, VT, true, isOpaque);<br>
}<br>
@@ -503,26 +504,27 @@ public:<br>
/// The forms that take a double should only be used for simple constants<br>
/// that can be exactly represented in VT. No checks are made.<br>
/// @{<br>
- SDValue getConstantFP(double Val, SDLoc DL, EVT VT, bool isTarget = false);<br>
- SDValue getConstantFP(const APFloat& Val, SDLoc DL, EVT VT,<br>
+ SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT,<br>
+ bool isTarget = false);<br>
+ SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,<br>
bool isTarget = false);<br>
- SDValue getConstantFP(const ConstantFP &CF, SDLoc DL, EVT VT,<br>
+ SDValue getConstantFP(const ConstantFP &CF, const SDLoc &DL, EVT VT,<br>
bool isTarget = false);<br>
- SDValue getTargetConstantFP(double Val, SDLoc DL, EVT VT) {<br>
+ SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {<br>
return getConstantFP(Val, DL, VT, true);<br>
}<br>
- SDValue getTargetConstantFP(const APFloat& Val, SDLoc DL, EVT VT) {<br>
+ SDValue getTargetConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT) {<br>
return getConstantFP(Val, DL, VT, true);<br>
}<br>
- SDValue getTargetConstantFP(const ConstantFP &Val, SDLoc DL, EVT VT) {<br>
+ SDValue getTargetConstantFP(const ConstantFP &Val, const SDLoc &DL, EVT VT) {<br>
return getConstantFP(Val, DL, VT, true);<br>
}<br>
/// @}<br>
<br>
- SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,<br>
+ SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,<br>
int64_t offset = 0, bool isTargetGA = false,<br>
unsigned char TargetFlags = 0);<br>
- SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,<br>
+ SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,<br>
int64_t offset = 0,<br>
unsigned char TargetFlags = 0) {<br>
return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);<br>
@@ -559,7 +561,7 @@ public:<br>
SDValue getBasicBlock(MachineBasicBlock *MBB);<br>
SDValue getBasicBlock(MachineBasicBlock *MBB, SDLoc dl);<br>
SDValue getExternalSymbol(const char *Sym, EVT VT);<br>
- SDValue getExternalSymbol(const char *Sym, SDLoc dl, EVT VT);<br>
+ SDValue getExternalSymbol(const char *Sym, const SDLoc &dl, EVT VT);<br>
SDValue getTargetExternalSymbol(const char *Sym, EVT VT,<br>
unsigned char TargetFlags = 0);<br>
SDValue getMCSymbol(MCSymbol *Sym, EVT VT);<br>
@@ -567,7 +569,7 @@ public:<br>
SDValue getValueType(EVT);<br>
SDValue getRegister(unsigned Reg, EVT VT);<br>
SDValue getRegisterMask(const uint32_t *RegMask);<br>
- SDValue getEHLabel(SDLoc dl, SDValue Root, MCSymbol *Label);<br>
+ SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label);<br>
SDValue getBlockAddress(const BlockAddress *BA, EVT VT,<br>
int64_t Offset = 0, bool isTarget = false,<br>
unsigned char TargetFlags = 0);<br>
@@ -577,7 +579,8 @@ public:<br>
return getBlockAddress(BA, VT, Offset, true, TargetFlags);<br>
}<br>
<br>
- SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) {<br>
+ SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg,<br>
+ SDValue N) {<br>
return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,<br>
getRegister(Reg, N.getValueType()), N);<br>
}<br>
@@ -585,7 +588,7 @@ public:<br>
// This version of the getCopyToReg method takes an extra operand, which<br>
// indicates that there is potentially an incoming glue value (if Glue is not<br>
// null) and that there should be a glue result.<br>
- SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N,<br>
+ SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N,<br>
SDValue Glue) {<br>
SDVTList VTs = getVTList(MVT::Other, MVT::Glue);<br>
SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };<br>
@@ -594,15 +597,15 @@ public:<br>
}<br>
<br>
// Similar to last getCopyToReg() except parameter Reg is a SDValue<br>
- SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N,<br>
- SDValue Glue) {<br>
+ SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N,<br>
+ SDValue Glue) {<br>
SDVTList VTs = getVTList(MVT::Other, MVT::Glue);<br>
SDValue Ops[] = { Chain, Reg, N, Glue };<br>
return getNode(ISD::CopyToReg, dl, VTs,<br>
makeArrayRef(Ops, Glue.getNode() ? 4 : 3));<br>
}<br>
<br>
- SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) {<br>
+ SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) {<br>
SDVTList VTs = getVTList(VT, MVT::Other);<br>
SDValue Ops[] = { Chain, getRegister(Reg, VT) };<br>
return getNode(ISD::CopyFromReg, dl, VTs, Ops);<br>
@@ -611,8 +614,8 @@ public:<br>
// This version of the getCopyFromReg method takes an extra operand, which<br>
// indicates that there is potentially an incoming glue value (if Glue is not<br>
// null) and that there should be a glue result.<br>
- SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT,<br>
- SDValue Glue) {<br>
+ SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT,<br>
+ SDValue Glue) {<br>
SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);<br>
SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };<br>
return getNode(ISD::CopyFromReg, dl, VTs,<br>
@@ -623,16 +626,16 @@ public:<br>
<br>
/// Returns the ConvertRndSat Note: Avoid using this node because it may<br>
/// disappear in the future and most targets don't support it.<br>
- SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy,<br>
- SDValue STy,<br>
- SDValue Rnd, SDValue Sat, ISD::CvtCode Code);<br>
+ SDValue getConvertRndSat(EVT VT, const SDLoc &dl, SDValue Val, SDValue DTy,<br>
+ SDValue STy, SDValue Rnd, SDValue Sat,<br>
+ ISD::CvtCode Code);<br>
<br>
/// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,<br>
/// which must be a vector type, must match the number of mask elements<br>
/// NumElts. An integer mask element equal to -1 is treated as undefined.<br>
- SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,<br>
+ SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,<br>
const int *MaskElts);<br>
- SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,<br>
+ SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,<br>
ArrayRef<int> MaskElts) {<br>
assert(VT.getVectorNumElements() == MaskElts.size() &&<br>
"Must have the same number of vector elements as mask elements!");<br>
@@ -643,7 +646,7 @@ public:<br>
/// which must be a vector type, must match the number of operands in Ops.<br>
/// The operands must have the same type as (or, for integers, a type wider<br>
/// than) VT's element type.<br>
- SDValue getBuildVector(EVT VT, SDLoc DL, ArrayRef<SDValue> Ops) {<br>
+ SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDValue> Ops) {<br>
// VerifySDNode (via InsertNode) checks BUILD_VECTOR later.<br>
return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);<br>
}<br>
@@ -651,7 +654,7 @@ public:<br>
/// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all<br>
/// elements. VT must be a vector type. Op's type must be the same as (or,<br>
/// for integers, a type wider than) VT's element type.<br>
- SDValue getSplatBuildVector(EVT VT, SDLoc DL, SDValue Op) {<br>
+ SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {<br>
// VerifySDNode (via InsertNode) checks BUILD_VECTOR later.<br>
if (Op.getOpcode() == ISD::UNDEF) {<br>
assert((VT.getVectorElementType() == Op.getValueType() ||<br>
@@ -679,52 +682,52 @@ public:<br>
<br>
/// Convert Op, which must be of integer type, to the<br>
/// integer type VT, by either any-extending or truncating it.<br>
- SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);<br>
+ SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);<br>
<br>
/// Convert Op, which must be of integer type, to the<br>
/// integer type VT, by either sign-extending or truncating it.<br>
- SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);<br>
+ SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);<br>
<br>
/// Convert Op, which must be of integer type, to the<br>
/// integer type VT, by either zero-extending or truncating it.<br>
- SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);<br>
+ SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);<br>
<br>
/// Return the expression required to zero extend the Op<br>
/// value assuming it was the smaller SrcTy value.<br>
- SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy);<br>
+ SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy);<br>
<br>
/// Return an operation which will any-extend the low lanes of the operand<br>
/// into the specified vector type. For example,<br>
/// this can convert a v16i8 into a v4i32 by any-extending the low four<br>
/// lanes of the operand from i8 to i32.<br>
- SDValue getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);<br>
+ SDValue getAnyExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);<br>
<br>
/// Return an operation which will sign extend the low lanes of the operand<br>
/// into the specified vector type. For example,<br>
/// this can convert a v16i8 into a v4i32 by sign extending the low four<br>
/// lanes of the operand from i8 to i32.<br>
- SDValue getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);<br>
+ SDValue getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);<br>
<br>
/// Return an operation which will zero extend the low lanes of the operand<br>
/// into the specified vector type. For example,<br>
/// this can convert a v16i8 into a v4i32 by zero extending the low four<br>
/// lanes of the operand from i8 to i32.<br>
- SDValue getZeroExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT);<br>
+ SDValue getZeroExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);<br>
<br>
/// Convert Op, which must be of integer type, to the integer type VT,<br>
/// by using an extension appropriate for the target's<br>
/// BooleanContent for type OpVT or truncating it.<br>
- SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT);<br>
+ SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT);<br>
<br>
/// Create a bitwise NOT operation as (XOR Val, -1).<br>
- SDValue getNOT(SDLoc DL, SDValue Val, EVT VT);<br>
+ SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);<br>
<br>
/// \brief Create a logical NOT operation as (XOR Val, BooleanOne).<br>
- SDValue getLogicalNOT(SDLoc DL, SDValue Val, EVT VT);<br>
+ SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);<br>
<br>
/// Return a new CALLSEQ_START node, which always must have a glue result<br>
/// (to ensure it's not CSE'd). CALLSEQ_START does not have a useful SDLoc.<br>
- SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL) {<br>
+ SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL) {<br>
SDVTList VTs = getVTList(MVT::Other, MVT::Glue);<br>
SDValue Ops[] = { Chain, Op };<br>
return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);<br>
@@ -734,7 +737,7 @@ public:<br>
/// glue result (to ensure it's not CSE'd).<br>
/// CALLSEQ_END does not have a useful SDLoc.<br>
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,<br>
- SDValue InGlue, SDLoc DL) {<br>
+ SDValue InGlue, const SDLoc &DL) {<br>
SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue);<br>
SmallVector<SDValue, 4> Ops;<br>
Ops.push_back(Chain);<br>
@@ -757,38 +760,38 @@ public:<br>
<br>
/// Gets or creates the specified node.<br>
///<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,<br>
ArrayRef<SDUse> Ops);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,<br>
ArrayRef<SDValue> Ops, const SDNodeFlags *Flags = nullptr);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, ArrayRef<EVT> ResultTys,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys,<br>
ArrayRef<SDValue> Ops);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,<br>
ArrayRef<SDValue> Ops);<br>
<br>
// Specialize based on number of operands.<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,<br>
- const SDNodeFlags *Flags = nullptr);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,<br>
- SDValue N3);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,<br>
- SDValue N3, SDValue N4);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,<br>
- SDValue N3, SDValue N4, SDValue N5);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,<br>
+ SDValue N2, const SDNodeFlags *Flags = nullptr);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,<br>
+ SDValue N2, SDValue N3);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,<br>
+ SDValue N2, SDValue N3, SDValue N4);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,<br>
+ SDValue N2, SDValue N3, SDValue N4, SDValue N5);<br>
<br>
// Specialize again based on number of operands for nodes with a VTList<br>
// rather than a single VT.<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N);<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,<br>
SDValue N2);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,<br>
SDValue N2, SDValue N3);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,<br>
SDValue N2, SDValue N3, SDValue N4);<br>
- SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,<br>
+ SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,<br>
SDValue N2, SDValue N3, SDValue N4, SDValue N5);<br>
<br>
/// Compute a TokenFactor to force all the incoming stack arguments to be<br>
@@ -796,24 +799,24 @@ public:<br>
/// stack arguments from being clobbered.<br>
SDValue getStackArgumentTokenFactor(SDValue Chain);<br>
<br>
- SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,<br>
+ SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,<br>
SDValue Size, unsigned Align, bool isVol, bool AlwaysInline,<br>
bool isTailCall, MachinePointerInfo DstPtrInfo,<br>
MachinePointerInfo SrcPtrInfo);<br>
<br>
- SDValue getMemmove(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,<br>
+ SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,<br>
SDValue Size, unsigned Align, bool isVol, bool isTailCall,<br>
MachinePointerInfo DstPtrInfo,<br>
MachinePointerInfo SrcPtrInfo);<br>
<br>
- SDValue getMemset(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,<br>
+ SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,<br>
SDValue Size, unsigned Align, bool isVol, bool isTailCall,<br>
MachinePointerInfo DstPtrInfo);<br>
<br>
/// Helper function to make it easier to build SetCC's if you just<br>
/// have an ISD::CondCode instead of an SDValue.<br>
///<br>
- SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,<br>
+ SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,<br>
ISD::CondCode Cond) {<br>
assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&<br>
"Cannot compare scalars to vectors");<br>
@@ -826,8 +829,8 @@ public:<br>
<br>
/// Helper function to make it easier to build Select's if you just<br>
/// have operands and don't want to check for vector.<br>
- SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond,<br>
- SDValue LHS, SDValue RHS) {<br>
+ SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS,<br>
+ SDValue RHS) {<br>
assert(LHS.getValueType() == RHS.getValueType() &&<br>
"Cannot use select on differing types");<br>
assert(VT.isVector() == LHS.getValueType().isVector() &&<br>
@@ -839,142 +842,137 @@ public:<br>
/// Helper function to make it easier to build SelectCC's if you<br>
/// just have an ISD::CondCode instead of an SDValue.<br>
///<br>
- SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS,<br>
- SDValue True, SDValue False, ISD::CondCode Cond) {<br>
+ SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True,<br>
+ SDValue False, ISD::CondCode Cond) {<br>
return getNode(ISD::SELECT_CC, DL, True.getValueType(),<br>
LHS, RHS, True, False, getCondCode(Cond));<br>
}<br>
<br>
/// VAArg produces a result and token chain, and takes a pointer<br>
/// and a source value as input.<br>
- SDValue getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,<br>
+ SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,<br>
SDValue SV, unsigned Align);<br>
<br>
/// Gets a node for an atomic cmpxchg op. There are two<br>
/// valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a<br>
/// chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded,<br>
/// a success flag (initially i1), and a chain.<br>
- SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs,<br>
- SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp,<br>
- MachinePointerInfo PtrInfo, unsigned Alignment,<br>
- AtomicOrdering SuccessOrdering,<br>
+ SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,<br>
+ SDVTList VTs, SDValue Chain, SDValue Ptr,<br>
+ SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo,<br>
+ unsigned Alignment, AtomicOrdering SuccessOrdering,<br>
AtomicOrdering FailureOrdering,<br>
SynchronizationScope SynchScope);<br>
- SDValue getAtomicCmpSwap(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTs,<br>
- SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp,<br>
- MachineMemOperand *MMO,<br>
+ SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,<br>
+ SDVTList VTs, SDValue Chain, SDValue Ptr,<br>
+ SDValue Cmp, SDValue Swp, MachineMemOperand *MMO,<br>
AtomicOrdering SuccessOrdering,<br>
AtomicOrdering FailureOrdering,<br>
SynchronizationScope SynchScope);<br>
<br>
/// Gets a node for an atomic op, produces result (if relevant)<br>
/// and chain and takes 2 operands.<br>
- SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,<br>
+ SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,<br>
SDValue Ptr, SDValue Val, const Value *PtrVal,<br>
unsigned Alignment, AtomicOrdering Ordering,<br>
SynchronizationScope SynchScope);<br>
- SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,<br>
+ SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,<br>
SDValue Ptr, SDValue Val, MachineMemOperand *MMO,<br>
- AtomicOrdering Ordering,<br>
- SynchronizationScope SynchScope);<br>
+ AtomicOrdering Ordering, SynchronizationScope SynchScope);<br>
<br>
/// Gets a node for an atomic op, produces result and chain and<br>
/// takes 1 operand.<br>
- SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT,<br>
+ SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT,<br>
SDValue Chain, SDValue Ptr, MachineMemOperand *MMO,<br>
- AtomicOrdering Ordering,<br>
- SynchronizationScope SynchScope);<br>
+ AtomicOrdering Ordering, SynchronizationScope SynchScope);<br>
<br>
/// Gets a node for an atomic op, produces result and chain and takes N<br>
/// operands.<br>
- SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,<br>
- ArrayRef<SDValue> Ops, MachineMemOperand *MMO,<br>
- AtomicOrdering SuccessOrdering,<br>
+ SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,<br>
+ SDVTList VTList, ArrayRef<SDValue> Ops,<br>
+ MachineMemOperand *MMO, AtomicOrdering SuccessOrdering,<br>
AtomicOrdering FailureOrdering,<br>
SynchronizationScope SynchScope);<br>
- SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,<br>
- ArrayRef<SDValue> Ops, MachineMemOperand *MMO,<br>
- AtomicOrdering Ordering, SynchronizationScope SynchScope);<br>
+ SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,<br>
+ SDVTList VTList, ArrayRef<SDValue> Ops,<br>
+ MachineMemOperand *MMO, AtomicOrdering Ordering,<br>
+ SynchronizationScope SynchScope);<br>
<br>
/// Creates a MemIntrinsicNode that may produce a<br>
/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,<br>
/// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not<br>
/// less than FIRST_TARGET_MEMORY_OPCODE.<br>
- SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,<br>
- ArrayRef<SDValue> Ops,<br>
- EVT MemVT, MachinePointerInfo PtrInfo,<br>
- unsigned Align = 0, bool Vol = false,<br>
- bool ReadMem = true, bool WriteMem = true,<br>
- unsigned Size = 0);<br>
-<br>
- SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,<br>
- ArrayRef<SDValue> Ops,<br>
- EVT MemVT, MachineMemOperand *MMO);<br>
+ SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,<br>
+ ArrayRef<SDValue> Ops, EVT MemVT,<br>
+ MachinePointerInfo PtrInfo, unsigned Align = 0,<br>
+ bool Vol = false, bool ReadMem = true,<br>
+ bool WriteMem = true, unsigned Size = 0);<br>
+<br>
+ SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,<br>
+ ArrayRef<SDValue> Ops, EVT MemVT,<br>
+ MachineMemOperand *MMO);<br>
<br>
/// Create a MERGE_VALUES node from the given operands.<br>
- SDValue getMergeValues(ArrayRef<SDValue> Ops, SDLoc dl);<br>
+ SDValue getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl);<br>
<br>
/// Loads are not normal binary operators: their result type is not<br>
/// determined by their operands, and they produce a value AND a token chain.<br>
///<br>
- SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,<br>
+ SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,<br>
MachinePointerInfo PtrInfo, bool isVolatile,<br>
bool isNonTemporal, bool isInvariant, unsigned Alignment,<br>
const AAMDNodes &AAInfo = AAMDNodes(),<br>
const MDNode *Ranges = nullptr);<br>
- SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,<br>
+ SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,<br>
MachineMemOperand *MMO);<br>
- SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,<br>
+ SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,<br>
SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo,<br>
- EVT MemVT, bool isVolatile,<br>
- bool isNonTemporal, bool isInvariant, unsigned Alignment,<br>
+ EVT MemVT, bool isVolatile, bool isNonTemporal,<br>
+ bool isInvariant, unsigned Alignment,<br>
const AAMDNodes &AAInfo = AAMDNodes());<br>
- SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,<br>
+ SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,<br>
SDValue Chain, SDValue Ptr, EVT MemVT,<br>
MachineMemOperand *MMO);<br>
- SDValue getIndexedLoad(SDValue OrigLoad, SDLoc dl, SDValue Base,<br>
+ SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base,<br>
SDValue Offset, ISD::MemIndexedMode AM);<br>
- SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,<br>
- EVT VT, SDLoc dl,<br>
- SDValue Chain, SDValue Ptr, SDValue Offset,<br>
- MachinePointerInfo PtrInfo, EVT MemVT,<br>
- bool isVolatile, bool isNonTemporal, bool isInvariant,<br>
- unsigned Alignment, const AAMDNodes &AAInfo = AAMDNodes(),<br>
+ SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,<br>
+ const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,<br>
+ MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile,<br>
+ bool isNonTemporal, bool isInvariant, unsigned Alignment,<br>
+ const AAMDNodes &AAInfo = AAMDNodes(),<br>
const MDNode *Ranges = nullptr);<br>
- SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,<br>
- EVT VT, SDLoc dl,<br>
- SDValue Chain, SDValue Ptr, SDValue Offset,<br>
+ SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,<br>
+ const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,<br>
EVT MemVT, MachineMemOperand *MMO);<br>
<br>
/// Helper function to build ISD::STORE nodes.<br>
- SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,<br>
+ SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,<br>
MachinePointerInfo PtrInfo, bool isVolatile,<br>
bool isNonTemporal, unsigned Alignment,<br>
const AAMDNodes &AAInfo = AAMDNodes());<br>
- SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,<br>
+ SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,<br>
MachineMemOperand *MMO);<br>
- SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,<br>
- MachinePointerInfo PtrInfo, EVT TVT,<br>
- bool isNonTemporal, bool isVolatile,<br>
- unsigned Alignment,<br>
+ SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,<br>
+ SDValue Ptr, MachinePointerInfo PtrInfo, EVT TVT,<br>
+ bool isNonTemporal, bool isVolatile, unsigned Alignment,<br>
const AAMDNodes &AAInfo = AAMDNodes());<br>
- SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,<br>
- EVT TVT, MachineMemOperand *MMO);<br>
- SDValue getIndexedStore(SDValue OrigStoe, SDLoc dl, SDValue Base,<br>
+ SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,<br>
+ SDValue Ptr, EVT TVT, MachineMemOperand *MMO);<br>
+ SDValue getIndexedStore(SDValue OrigStoe, const SDLoc &dl, SDValue Base,<br>
SDValue Offset, ISD::MemIndexedMode AM);<br>
<br>
/// Returns sum of the base pointer and offset.<br>
- SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc DL);<br>
+ SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc &DL);<br>
<br>
- SDValue getMaskedLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,<br>
+ SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,<br>
SDValue Mask, SDValue Src0, EVT MemVT,<br>
MachineMemOperand *MMO, ISD::LoadExtType);<br>
- SDValue getMaskedStore(SDValue Chain, SDLoc dl, SDValue Val,<br>
+ SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val,<br>
SDValue Ptr, SDValue Mask, EVT MemVT,<br>
MachineMemOperand *MMO, bool IsTrunc);<br>
- SDValue getMaskedGather(SDVTList VTs, EVT VT, SDLoc dl,<br>
+ SDValue getMaskedGather(SDVTList VTs, EVT VT, const SDLoc &dl,<br>
ArrayRef<SDValue> Ops, MachineMemOperand *MMO);<br>
- SDValue getMaskedScatter(SDVTList VTs, EVT VT, SDLoc dl,<br>
+ SDValue getMaskedScatter(SDVTList VTs, EVT VT, const SDLoc &dl,<br>
ArrayRef<SDValue> Ops, MachineMemOperand *MMO);<br>
/// Construct a node to track a Value* through the backend.<br>
SDValue getSrcValue(const Value *v);<br>
@@ -987,8 +985,8 @@ public:<br>
SDValue getBitcast(EVT VT, SDValue V);<br>
<br>
/// Return an AddrSpaceCastSDNode.<br>
- SDValue getAddrSpaceCast(SDLoc dl, EVT VT, SDValue Ptr,<br>
- unsigned SrcAS, unsigned DestAS);<br>
+ SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS,<br>
+ unsigned DestAS);<br>
<br>
/// Return the specified value casted to<br>
/// the target's desired shift amount type.<br>
@@ -1057,45 +1055,46 @@ public:<br>
/// Note that getMachineNode returns the resultant node. If there is already<br>
/// a node of the specified opcode and operands, it returns that node instead<br>
/// of the current one.<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,<br>
SDValue Op1);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,<br>
SDValue Op1, SDValue Op2);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,<br>
SDValue Op1, SDValue Op2, SDValue Op3);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,<br>
ArrayRef<SDValue> Ops);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- SDValue Op1);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- SDValue Op1, SDValue Op2);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- SDValue Op1, SDValue Op2, SDValue Op3);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- ArrayRef<SDValue> Ops);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- EVT VT3, SDValue Op1, SDValue Op2);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- EVT VT3, SDValue Op1, SDValue Op2,<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, SDValue Op1);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, SDValue Op1, SDValue Op2);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, ArrayRef<SDValue> Ops);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, EVT VT3, SDValue Op1, SDValue Op2);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, EVT VT3, SDValue Op1, SDValue Op2,<br>
SDValue Op3);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- EVT VT3, ArrayRef<SDValue> Ops);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2,<br>
- EVT VT3, EVT VT4, ArrayRef<SDValue> Ops);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl,<br>
- ArrayRef<EVT> ResultTys,<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,<br>
+ EVT VT2, EVT VT3, EVT VT4,<br>
ArrayRef<SDValue> Ops);<br>
- MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, SDVTList VTs,<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl,<br>
+ ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops);<br>
+ MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, SDVTList VTs,<br>
ArrayRef<SDValue> Ops);<br>
<br>
/// A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.<br>
- SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT,<br>
+ SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,<br>
SDValue Operand);<br>
<br>
/// A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.<br>
- SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,<br>
+ SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,<br>
SDValue Operand, SDValue Subreg);<br>
<br>
/// Get the specified node if it's already available, or else return NULL.<br>
@@ -1104,16 +1103,17 @@ public:<br>
<br>
/// Creates a SDDbgValue node.<br>
SDDbgValue *getDbgValue(MDNode *Var, MDNode *Expr, SDNode *N, unsigned R,<br>
- bool IsIndirect, uint64_t Off, DebugLoc DL,<br>
+ bool IsIndirect, uint64_t Off, const DebugLoc &DL,<br>
unsigned O);<br>
<br>
/// Constant<br>
SDDbgValue *getConstantDbgValue(MDNode *Var, MDNode *Expr, const Value *C,<br>
- uint64_t Off, DebugLoc DL, unsigned O);<br>
+ uint64_t Off, const DebugLoc &DL, unsigned O);<br>
<br>
/// FrameIndex<br>
SDDbgValue *getFrameIndexDbgValue(MDNode *Var, MDNode *Expr, unsigned FI,<br>
- uint64_t Off, DebugLoc DL, unsigned O);<br>
+ uint64_t Off, const DebugLoc &DL,<br>
+ unsigned O);<br>
<br>
/// Remove the specified node from the system. If any of its<br>
/// operands then becomes dead, remove them as well. Inform UpdateListener<br>
@@ -1252,20 +1252,20 @@ public:<br>
const GlobalAddressSDNode *GA,<br>
const SDNode *N2);<br>
<br>
- SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,<br>
+ SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,<br>
SDNode *Cst1, SDNode *Cst2);<br>
<br>
- SDValue FoldConstantArithmetic(unsigned Opcode, SDLoc DL, EVT VT,<br>
+ SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,<br>
const ConstantSDNode *Cst1,<br>
const ConstantSDNode *Cst2);<br>
<br>
- SDValue FoldConstantVectorArithmetic(unsigned Opcode, SDLoc DL,<br>
- EVT VT, ArrayRef<SDValue> Ops,<br>
+ SDValue FoldConstantVectorArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,<br>
+ ArrayRef<SDValue> Ops,<br>
const SDNodeFlags *Flags = nullptr);<br>
<br>
/// Constant fold a setcc to true or false.<br>
- SDValue FoldSetCC(EVT VT, SDValue N1,<br>
- SDValue N2, ISD::CondCode Cond, SDLoc dl);<br>
+ SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond,<br>
+ const SDLoc &dl);<br>
<br>
/// Return true if the sign bit of Op is known to be zero.<br>
/// We use this predicate to simplify operations downstream.<br>
@@ -1389,8 +1389,9 @@ private:<br>
<br>
void allnodes_clear();<br>
<br>
- SDNode *GetBinarySDNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N1,<br>
- SDValue N2, const SDNodeFlags *Flags = nullptr);<br>
+ SDNode *GetBinarySDNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,<br>
+ SDValue N1, SDValue N2,<br>
+ const SDNodeFlags *Flags = nullptr);<br>
<br>
/// Look up the node specified by ID in CSEMap. If it exists, return it. If<br>
/// not, return the insertion token that will make insertion faster. This<br>
@@ -1401,7 +1402,7 @@ private:<br>
/// Look up the node specified by ID in CSEMap. If it exists, return it. If<br>
/// not, return the insertion token that will make insertion faster. Performs<br>
/// additional processing for constant nodes.<br>
- SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, SDLoc DL,<br>
+ SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, const SDLoc &DL,<br>
void *&InsertPos);<br>
<br>
/// List of non-single value types.<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=272512&r1=272511&r2=272512&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=272512&r1=272511&r2=272512&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Sun Jun 12 10:39:02 2016<br>
@@ -210,8 +210,8 @@ protected:<br>
<br>
/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated<br>
/// by tblgen. Others should not call it.<br>
- void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, SDLoc DL);<br>
-<br>
+ void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,<br>
+ const SDLoc &DL);<br>
<br>
public:<br>
// Calls to these predicates are generated by tblgen.<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=272512&r1=272511&r2=272512&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=272512&r1=272511&r2=272512&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Sun Jun 12 10:39:02 2016<br>
@@ -847,8 +847,8 @@ public:<br>
if (I)<br>
DL = I->getDebugLoc();<br>
}<br>
- unsigned getIROrder() { return IROrder; }<br>
- DebugLoc getDebugLoc() { return DL; }<br>
+ unsigned getIROrder() const { return IROrder; }<br>
+ const DebugLoc &getDebugLoc() const { return DL; }<br>
};<br>
<br>
<br>
@@ -952,8 +952,8 @@ static bool isBinOpWithFlags(unsigned Op<br>
class BinaryWithFlagsSDNode : public SDNode {<br>
public:<br>
SDNodeFlags Flags;<br>
- BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,<br>
- const SDNodeFlags &NodeFlags)<br>
+ BinaryWithFlagsSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,<br>
+ SDVTList VTs, const SDNodeFlags &NodeFlags)<br>
: SDNode(Opc, Order, dl, VTs), Flags(NodeFlags) {}<br>
static bool classof(const SDNode *N) {<br>
return isBinOpWithFlags(N->getOpcode());<br>
@@ -992,8 +992,8 @@ private:<br>
unsigned DestAddrSpace;<br>
<br>
public:<br>
- AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT, unsigned SrcAS,<br>
- unsigned DestAS);<br>
+ AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,<br>
+ unsigned SrcAS, unsigned DestAS);<br>
<br>
unsigned getSrcAddressSpace() const { return SrcAddrSpace; }<br>
unsigned getDestAddressSpace() const { return DestAddrSpace; }<br>
@@ -1014,7 +1014,7 @@ protected:<br>
MachineMemOperand *MMO;<br>
<br>
public:<br>
- MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,<br>
+ MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,<br>
EVT MemoryVT, MachineMemOperand *MMO);<br>
<br>
bool readMem() const { return MMO->isLoad(); }<br>
@@ -1146,7 +1146,7 @@ class AtomicSDNode : public MemSDNode {<br>
}<br>
<br>
public:<br>
- AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL,<br>
+ AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,<br>
EVT MemVT, MachineMemOperand *MMO,<br>
AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering,<br>
SynchronizationScope SynchScope)<br>
@@ -1198,8 +1198,8 @@ public:<br>
/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.<br>
class MemIntrinsicSDNode : public MemSDNode {<br>
public:<br>
- MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,<br>
- EVT MemoryVT, MachineMemOperand *MMO)<br>
+ MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,<br>
+ SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)<br>
: MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {<br>
SubclassData |= 1u << 13;<br>
}<br>
@@ -1228,7 +1228,7 @@ class ShuffleVectorSDNode : public SDNod<br>
const int *Mask;<br>
protected:<br>
friend class SelectionDAG;<br>
- ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, const int *M)<br>
+ ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)<br>
: SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}<br>
<br>
public:<br>
@@ -1277,9 +1277,10 @@ class ConstantSDNode : public SDNode {<br>
const ConstantInt *Value;<br>
friend class SelectionDAG;<br>
ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val,<br>
- DebugLoc DL, EVT VT)<br>
- : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,<br>
- 0, DL, getSDVTList(VT)), Value(val) {<br>
+ const DebugLoc &DL, EVT VT)<br>
+ : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DL,<br>
+ getSDVTList(VT)),<br>
+ Value(val) {<br>
SubclassData |= (uint16_t)isOpaque;<br>
}<br>
public:<br>
@@ -1304,10 +1305,12 @@ public:<br>
class ConstantFPSDNode : public SDNode {<br>
const ConstantFP *Value;<br>
friend class SelectionDAG;<br>
- ConstantFPSDNode(bool isTarget, const ConstantFP *val, DebugLoc DL, EVT VT)<br>
- : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,<br>
- 0, DL, getSDVTList(VT)), Value(val) {<br>
- }<br>
+ ConstantFPSDNode(bool isTarget, const ConstantFP *val, const DebugLoc &DL,<br>
+ EVT VT)<br>
+ : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0, DL,<br>
+ getSDVTList(VT)),<br>
+ Value(val) {}<br>
+<br>
public:<br>
<br>
const APFloat& getValueAPF() const { return Value->getValueAPF(); }<br>
@@ -1367,9 +1370,10 @@ class GlobalAddressSDNode : public SDNod<br>
int64_t Offset;<br>
unsigned char TargetFlags;<br>
friend class SelectionDAG;<br>
- GlobalAddressSDNode(unsigned Opc, unsigned Order, DebugLoc DL,<br>
+ GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,<br>
const GlobalValue *GA, EVT VT, int64_t o,<br>
unsigned char TargetFlags);<br>
+<br>
public:<br>
<br>
const GlobalValue *getGlobal() const { return TheGlobal; }<br>
@@ -1667,7 +1671,7 @@ public:<br>
class EHLabelSDNode : public SDNode {<br>
MCSymbol *Label;<br>
friend class SelectionDAG;<br>
- EHLabelSDNode(unsigned Order, DebugLoc dl, MCSymbol *L)<br>
+ EHLabelSDNode(unsigned Order, const DebugLoc &dl, MCSymbol *L)<br>
: SDNode(ISD::EH_LABEL, Order, dl, getSDVTList(MVT::Other)), Label(L) {}<br>
<br>
public:<br>
@@ -1734,7 +1738,7 @@ public:<br>
class CvtRndSatSDNode : public SDNode {<br>
ISD::CvtCode CvtCode;<br>
friend class SelectionDAG;<br>
- explicit CvtRndSatSDNode(EVT VT, unsigned Order, DebugLoc dl,<br>
+ explicit CvtRndSatSDNode(EVT VT, unsigned Order, const DebugLoc &dl,<br>
ISD::CvtCode Code)<br>
: SDNode(ISD::CONVERT_RNDSAT, Order, dl, getSDVTList(VT)), CvtCode(Code) {<br>
}<br>
@@ -1768,10 +1772,10 @@ public:<br>
/// Base class for LoadSDNode and StoreSDNode<br>
class LSBaseSDNode : public MemSDNode {<br>
public:<br>
- LSBaseSDNode(ISD::</blockquote></div>