[PATCH] D21061: [ARM] Remove exit-on-error flag from test (PR27765)

[Diana Picus via llvm-commits]

rovka updated this revision to Diff 60046.
rovka added a comment.

Updated the test to use something other than undef as input too. This way we can test 2 different code paths (the one for undef is a bit special because it really doesn't create a bitcast node, it just creates an undef with the type we're bitcasting to). With this change, we're testing something a bit more realistic, and the fix still seems to work.

I can't find any tests for this error on other targets. Should I try to add one at least for X86?


http://reviews.llvm.org/D21061

Files:
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll

Index: test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
===================================================================
--- test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
+++ test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
@@ -1,10 +1,11 @@
-; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 -exit-on-error %s -o - 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - 2>&1 | FileCheck %s
 
 ; Check for error message:
 ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
 
 define hidden void @f(i32* %corr, i32 %order) nounwind ssp {
-  tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, <2 x i64>* undef) nounwind, !srcloc !0
+  tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, i32 %order) nounwind, !srcloc !0
   ret void
 }
 
Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -446,9 +446,11 @@
          "Failed to tile the value with PartVT!");
 
   if (NumParts == 1) {
-    if (PartEVT != ValueVT)
+    if (PartEVT != ValueVT) {
       diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
                                         "scalar-to-vector conversion failed");
+      Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
+    }
 
     Parts[0] = Val;
     return;


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