[PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions

[Hal Finkel via llvm-commits]

----- Original Message -----
> From: "Chuang-Yu Cheng" <cycheng at multicorewareinc.com>
> To: tjablin at gmail.com, amehsan at ca.ibm.com, cycheng at multicorewareinc.com, "nemanja i ibm" <nemanja.i.ibm at gmail.com>,
> hfinkel at anl.gov
> Cc: llvm-commits at lists.llvm.org
> Sent: Wednesday, June 1, 2016 2:58:55 AM
> Subject: Re: [PATCH] D20310: Teach LLVM about Power 9 D-Form VSX Instructions
> 
> cycheng added a comment.
> 
> > Thanks for working on this. I'd really like to see a unified
> > solution here, both for this and for the high half of the VSX
> > register file in general (i.e. using this same scheme to eliminate
> > the VSRH registers).
> 
> 
> Let me try again : )
> 
> So the unified solution, by my understanding, is: we should not
> define a new register class that is actually alias with existing
> register class, we can use customized instruction flags and custom
> c++ code to handle their difference part, e.g. name. Benefits I can
> image are: we don't have to teach backend that the two register
> class are the same, we can simplify register class hierarchy.

Yes, except that I'm not sure that we want to remove the register classes, just the register definitions themselves. This makes the change smaller, and also does not force us to add VSX-only data types to the Altivec register classes. In short, add VR0-31 directly to VSHRC. Does that make sense? Then you'll need some, but not all, of the changes you outline below.

Thanks again,
Hal

> 
> Our current register hierarchy:
> 
> - FPR (64-bit float register): F0 - http://reviews.llvm.org/F31 (f0 -
> f31)
> - VF (64-bit VSX register): VF0 - VF31 (vs32 - vs63)
> - VR (128-bit Altivec register): V0 - V31 (v0 - v31), overlap with VF
> (vs32 - vs63)
> - VSRL (128-bit VSX register): VSL0 - VSL31 (vs0 - vs31), overlap
> with FPR (f0 - f31)
> - VSRH (128-bit VSX register): VSH0 - VSH31 (vs32 - vs63), overlap
> with VR (v0 - v31)
> 
> Our current register class:
> 
> - F8RC: [f64] F0 - http://reviews.llvm.org/F31
> - VFRC: [f64] VF0 - VF31
> - VRRC: [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32] V0 - V31
> - VSLRC: [v4i32,v4f32,v2f64,v2i64] VSL0 - VSL31
> - VSHRC:[v4i32,v4f32,v2f64,v2i64] VSH0 - VSH31
> - VSRC: [v4i32,v4f32,v2f64,v2i64] VSLRC+VSHRC
> - VSFRC: [f64] F8RC, VFRC
> - VSSRC: [f32] F8RC, VFRC
> 
> I will remove VSRH, and below is my imaged modification:
> 
> //`In PPCRegisterInfo.td`//:
> 
> - Eliminate all VSRH and related register definitions
> 
>   class VSRH<VR SubReg, string n> : PPCReg<n> { ... }
>   
>   foreach Index = 0-31 in {
>     def VSH#Index : VSRH<!cast<VR>("V"#Index), "vs" # !add(Index,
>     32)>,
>                     DwarfRegAlias<!cast<VR>("V"#Index)>;
>   }
>   
>   def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
>                             (add VSH2, VSH3, VSH4, VSH5, VSH0, VSH1,
>                             VSH6, VSH7, ... )>;
> 
> - For VSRC, change VSHRC to VFRC
>   - I can image that we will also eliminate some code in
>   PPCVSXCopy.cpp, because we won't have this copy: //"VSRC.VSHRC
>   <---> VSFRC.VFRC"//
> 
>   def VSRC  : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
>                             (add VSLRC, VFRC)>;
> 
> - Change VF's definition:
> 
>   foreach Index = 0-31 in {
>     def VF#Index : VF<Index, "v" #Index>,
>                    DwarfRegNum<[!add(Index, 77), !add(Index, 77)];
>   }
> 
> - Add **v2f64** to VRRC's supported types
> - Because we eliminate VSHRC, so we should add its v2f64 to VRRC
> 
>   def VRRC : RegisterClass<"PPC",
>   [v16i8,v8i16,v4i32,v2i64,v2f64,v1i128,v4f32], 128,
> 
> //`In PPCISelLowering.cpp/PPCCallingConv.td`//
> 
> - revert changes of llvm c9de9e60b90 (r205041)
> 
>   change1:
>           case MVT::v2f64:
>           case MVT::v2i64:
>             RC = &PPC::VSHRCRegClass; => VRRCRegClass;
>   
>   change2:
>           MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) : => remove
>           (4 places)
>   
>   change3:
>     remove:
>       CCIfType<[v2f64, v2i64], CCAssignToReg<[VSH2]>>
>       CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
>                CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7,
>                VSH8, VSH9]>>>
>   
>     add v2f64, v2i64 back to [v16i8, v8i16, v4i32, v4f32]
> 
> In PPCAsmPrinter.cpp/PPCInstPrinter.cpp
> 
>   printOperand()
>      if the register belongs to upper VSX registers (and now we use
>      VFRC to represent it),
>      we need translate it from v0-v31 to vs32-vs63
> 
> //`In
> PPCAsmParser.cpp/PPCDisassembler.cpp/PPCRegisterInfo.cpp/PPCVSXCopy.cpp`//
> 
> - Just remove VSH related code
> 
> 
> http://reviews.llvm.org/D20310
> 
> 
> 
> 

-- 
Hal Finkel
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory