[PATCH] D21062: [mips][mips16] Fix machine verifier errors about incorrect register classes on load/stores.

[Daniel Sanders via llvm-commits]

dsanders created this revision.
dsanders added a reviewer: sdardis.
dsanders added a subscriber: llvm-commits.
Herald added subscribers: sdardis, dsanders.

[ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore
lower frameindex nodes such that there is a copy to a CPU16Regs register. This
is now done consistently using a separate addressing mode that does not
permit frameindex nodes.

As part of this I've had to remove an optimization that reduced the number of
instructions needed to work around the lack of sp-relative addresses on [ls][bh]
and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as
a copy of the stack pointer and it's implementation was the root cause of many
of the register vs register class mismatches.

lw/sw can use sp-relative addresses but we ought to ensure that we use the
correct version of lw/sw internally for things like IAS. This is not currently
the case and this change does not fix this. However, this change does clean it
up sufficiently well to fix the machine verifier failures.

Also removed irrelevant functions from stchar.ll.

http://reviews.llvm.org/D21062

Files:
  lib/Target/Mips/Mips16ISelDAGToDAG.cpp
  lib/Target/Mips/Mips16ISelDAGToDAG.h
  lib/Target/Mips/Mips16InstrInfo.td
  lib/Target/Mips/MipsISelDAGToDAG.cpp
  lib/Target/Mips/MipsISelDAGToDAG.h
  lib/Target/Mips/MipsMachineFunction.cpp
  lib/Target/Mips/MipsMachineFunction.h
  test/CodeGen/Mips/stchar.ll
  test/CodeGen/Mips/stldst.ll
  test/CodeGen/Mips/tailcall.ll

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