[llvm] r270594 - [AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
Konstantin Zhuravlyov via llvm-commits
llvm-commits at lists.llvm.org
Tue May 24 11:37:19 PDT 2016
Author: kzhuravl
Date: Tue May 24 13:37:18 2016
New Revision: 270594
URL: http://llvm.org/viewvc/llvm-project?rev=270594&view=rev
Log:
[AMDGPU][NFC] Rename ReserveTrapVGPRs -> ReserveRegs
Differential Revision: http://reviews.llvm.org/D20081
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPU.td?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPU.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPU.td Tue May 24 13:37:18 2016
@@ -328,11 +328,11 @@ def FeatureDebuggerInsertNops : Subtarge
"Insert one nop instruction for each high level source statement"
>;
-def FeatureDebuggerReserveTrapRegs : SubtargetFeature<
- "amdgpu-debugger-reserve-trap-regs",
- "DebuggerReserveTrapVGPRs",
+def FeatureDebuggerReserveRegs : SubtargetFeature<
+ "amdgpu-debugger-reserve-regs",
+ "DebuggerReserveRegs",
"true",
- "Reserve VGPRs for trap handler usage"
+ "Reserve registers for debugger usage"
>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Tue May 24 13:37:18 2016
@@ -435,12 +435,13 @@ void AMDGPUAsmPrinter::getSIProgramInfo(
MaxSGPR += ExtraSGPRs;
- // Update necessary Reserved* fields and max VGPRs used if
- // "amdgpu-debugger-reserve-trap-regs" attribute was specified.
- if (STM.debuggerReserveTrapVGPRs()) {
+ // Record first reserved register and reserved register count fields, and
+ // update max register counts if "amdgpu-debugger-reserve-regs" attribute was
+ // specified.
+ if (STM.debuggerReserveRegs()) {
ProgInfo.ReservedVGPRFirst = MaxVGPR + 1;
- ProgInfo.ReservedVGPRCount = MFI->getDebuggerReserveTrapVGPRCount();
- MaxVGPR += MFI->getDebuggerReserveTrapVGPRCount();
+ ProgInfo.ReservedVGPRCount = MFI->getDebuggerReservedVGPRCount();
+ MaxVGPR += MFI->getDebuggerReservedVGPRCount();
}
// We found the maximum register index. They start at 0, so add one to get the
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.cpp Tue May 24 13:37:18 2016
@@ -98,7 +98,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const T
LDSBankCount(0),
IsaVersion(ISAVersion0_0_0),
EnableSIScheduler(false),
- DebuggerInsertNops(false), DebuggerReserveTrapVGPRs(false),
+ DebuggerInsertNops(false), DebuggerReserveRegs(false),
FrameLowering(nullptr),
GISel(),
InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Tue May 24 13:37:18 2016
@@ -96,7 +96,7 @@ private:
unsigned IsaVersion;
bool EnableSIScheduler;
bool DebuggerInsertNops;
- bool DebuggerReserveTrapVGPRs;
+ bool DebuggerReserveRegs;
std::unique_ptr<AMDGPUFrameLowering> FrameLowering;
std::unique_ptr<AMDGPUTargetLowering> TLInfo;
@@ -319,8 +319,8 @@ public:
return DebuggerInsertNops;
}
- bool debuggerReserveTrapVGPRs() const {
- return DebuggerReserveTrapVGPRs;
+ bool debuggerReserveRegs() const {
+ return DebuggerReserveRegs;
}
bool dumpCode() const {
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Tue May 24 13:37:18 2016
@@ -49,7 +49,7 @@ SIMachineFunctionInfo::SIMachineFunction
PSInputAddr(0),
ReturnsVoid(true),
MaximumWorkGroupSize(0),
- DebuggerReserveTrapVGPRCount(0),
+ DebuggerReservedVGPRCount(0),
LDSWaveSpillSize(0),
PSInputEna(0),
NumUserSGPRs(0),
@@ -134,8 +134,8 @@ SIMachineFunctionInfo::SIMachineFunction
else
MaximumWorkGroupSize = ST.getWavefrontSize();
- if (ST.debuggerReserveTrapVGPRs())
- DebuggerReserveTrapVGPRCount = 4;
+ if (ST.debuggerReserveRegs())
+ DebuggerReservedVGPRCount = 4;
}
unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h Tue May 24 13:37:18 2016
@@ -62,8 +62,8 @@ class SIMachineFunctionInfo final : publ
unsigned MaximumWorkGroupSize;
- // Number of reserved VGPRs for trap handler usage.
- unsigned DebuggerReserveTrapVGPRCount;
+ // Number of reserved VGPRs for debugger usage.
+ unsigned DebuggerReservedVGPRCount;
public:
// FIXME: Make private
@@ -329,8 +329,9 @@ public:
ReturnsVoid = Value;
}
- unsigned getDebuggerReserveTrapVGPRCount() const {
- return DebuggerReserveTrapVGPRCount;
+ /// \returns Number of reserved VGPRs for debugger usage.
+ unsigned getDebuggerReservedVGPRCount() const {
+ return DebuggerReservedVGPRCount;
}
unsigned getMaximumWorkGroupSize(const MachineFunction &MF) const;
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Tue May 24 13:37:18 2016
@@ -193,12 +193,12 @@ BitVector SIRegisterInfo::getReservedReg
assert(!isSubRegister(ScratchRSrcReg, ScratchWaveOffsetReg));
}
- // Reserve VGPRs for trap handler usage if "amdgpu-debugger-reserve-trap-regs"
+ // Reserve registers for debugger usage if "amdgpu-debugger-reserve-trap-regs"
// attribute was specified.
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
- if (ST.debuggerReserveTrapVGPRs()) {
+ if (ST.debuggerReserveRegs()) {
unsigned ReservedVGPRFirst =
- MaxWorkGroupVGPRCount - MFI->getDebuggerReserveTrapVGPRCount();
+ MaxWorkGroupVGPRCount - MFI->getDebuggerReservedVGPRCount();
for (unsigned i = ReservedVGPRFirst; i < MaxWorkGroupVGPRCount; ++i) {
unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
reserveRegisterTuples(Reserved, Reg);
Modified: llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll?rev=270594&r1=270593&r2=270594&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/debugger-reserve-regs.ll Tue May 24 13:37:18 2016
@@ -1,8 +1,6 @@
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-trap-regs -verify-machineinstrs < %s | FileCheck %s
-
+; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s
; CHECK: reserved_vgpr_first = {{[0-9]+}}
; CHECK-NEXT: reserved_vgpr_count = 4
-
; CHECK: ReservedVGPRFirst: {{[0-9]+}}
; CHECK-NEXT: ReservedVGPRCount: 4
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