[llvm] r268744 - [AArch64] Decouple zero store promotion from narrow ld merge. NFC.

[Jun Bum Lim via llvm-commits]

Author: junbuml
Date: Fri May  6 10:08:57 2016
New Revision: 268744

URL: http://llvm.org/viewvc/llvm-project?rev=268744&view=rev
Log:
[AArch64] Decouple zero store promotion from narrow ld merge. NFC.

Summary: This change refactors to decouple the zero store promotion from the narrow ld merge and add a flag (enable-narrow-ld-merge=true) to control the narrow ld merge optimization.

Reviewers: jmolloy, t.p.northover, mcrosier

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D19885

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp?rev=268744&r1=268743&r2=268744&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Fri May  6 10:08:57 2016
@@ -51,6 +51,10 @@ static cl::opt<unsigned> LdStLimit("aarc
 static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
                                      cl::Hidden);
 
+static cl::opt<bool> EnableNarrowLdMerge("enable-narrow-ld-merge", cl::Hidden,
+                                         cl::init(true),
+                                         cl::desc("Enable narrow load merge"));
+
 namespace llvm {
 void initializeAArch64LoadStoreOptPass(PassRegistry &);
 }
@@ -614,11 +618,14 @@ static bool isLdOffsetInRangeOfSt(Machin
          (UnscaledLdOffset + LoadSize <= (UnscaledStOffset + StoreSize));
 }
 
-static bool isPromotableZeroStoreOpcode(MachineInstr *MI) {
-  unsigned Opc = MI->getOpcode();
+static bool isPromotableZeroStoreOpcode(unsigned Opc) {
   return isNarrowStore(Opc) || Opc == AArch64::STRWui || Opc == AArch64::STURWi;
 }
 
+static bool isPromotableZeroStoreOpcode(MachineInstr *MI) {
+  return isPromotableZeroStoreOpcode(MI->getOpcode());
+}
+
 static bool isPromotableZeroStoreInst(MachineInstr *MI) {
   return (isPromotableZeroStoreOpcode(MI)) &&
          getLdStRegOp(MI).getReg() == AArch64::WZR;
@@ -1722,36 +1729,17 @@ bool AArch64LoadStoreOpt::optimizeBlock(
   for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
        enableNarrowLdOpt && MBBI != E;) {
     MachineInstr *MI = MBBI;
-    switch (MI->getOpcode()) {
-    default:
-      // Just move on to the next instruction.
-      ++MBBI;
-      break;
-    // Scaled instructions.
-    case AArch64::LDRBBui:
-    case AArch64::LDRHHui:
-    case AArch64::LDRSBWui:
-    case AArch64::LDRSHWui:
-    case AArch64::STRBBui:
-    case AArch64::STRHHui:
-    case AArch64::STRWui:
-    // Unscaled instructions.
-    case AArch64::LDURBBi:
-    case AArch64::LDURHHi:
-    case AArch64::LDURSBWi:
-    case AArch64::LDURSHWi:
-    case AArch64::STURBBi:
-    case AArch64::STURHHi:
-    case AArch64::STURWi: {
+    unsigned Opc = MI->getOpcode();
+    if (isPromotableZeroStoreOpcode(Opc) ||
+        (EnableNarrowLdMerge && isNarrowLoad(Opc))) {
       if (tryToMergeLdStInst(MBBI)) {
         Modified = true;
-        break;
-      }
+      } else
+        ++MBBI;
+    } else
       ++MBBI;
-      break;
-    }
-    }
   }
+
   // 3) Find loads and stores that can be merged into a single load or store
   //    pair instruction.
   //      e.g.,