[PATCH] D18352: [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions

[Simon Dardis via llvm-commits]

sdardis requested changes to this revision.
sdardis added a comment.
This revision now requires changes to proceed.

One change and one nit. The inheritance order needs to be changed so that the various fields of the instruction records get set correctly. Comments inlined.


================
Comment at: lib/Target/Mips/MicroMips32r6InstrFormats.td:982
@@ +981,3 @@
+
+class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct> {
+  bits<5> ft;
----------------
This class needs to inherit from MMR6Arch, as the current ordering does not set the Arch and BaseOpcode properly. The inheritance ordering should be similar to that of the existing microMIPSR6 branches, such as BGEC_MMR6.

================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:1140-1142
@@ +1139,5 @@
+    BRANCH_DESC_BASE {
+  dag InOperandList = (ins COP2Opnd:$ft, brtarget_mm:$offset);
+  dag OutOperandList = (outs);
+  string AsmString = !strconcat(opstr, "\t$ft, $offset");
+  list<Register> Defs = [AT];
----------------
As coprocessor 2 is implementation dependant, $ft should be $rt.


http://reviews.llvm.org/D18352