[PATCH] D18352: [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions

[Zlatko Buljan via llvm-commits]

zbuljan updated this revision to Diff 56124.
zbuljan added a comment.

Used only one format class POOL32I_BRANCH_COP_1_2_FM_MMR6 (other one was redundant so it is deleted).
Modified desc. class BRANCH_COP1_MMR6_DESC_BASE to inherit the relevant parameterised InstSE<> class.
Register $at is now defined in both desc. classes (BRANCH_COP1_MMR6_DESC_BASE and BRANCH_COP2_MMR6_DESC_BASE).
Removed redundant tests and added additional invalid tests.


http://reviews.llvm.org/D18352

Files:
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  lib/Target/Mips/MicroMips32r6InstrFormats.td
  lib/Target/Mips/MicroMips32r6InstrInfo.td
  lib/Target/Mips/Mips32r6InstrInfo.td
  test/MC/Disassembler/Mips/micromips32r6/valid.txt
  test/MC/Disassembler/Mips/micromips64r6/valid.txt
  test/MC/Mips/micromips32r6/invalid.s
  test/MC/Mips/micromips32r6/valid.s
  test/MC/Mips/micromips64r6/invalid.s
  test/MC/Mips/micromips64r6/valid.s

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