[PATCH] D19805: [SelectionDAG] BITREVERSE vector legalization of bit operations

[Simon Pilgrim via llvm-commits]

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Vector bit operations are typically promoted instead of having custom lowering. This patch changes the isOperationLegalOrCustom tests for vector AND/OR operations to use isOperationLegalOrPromote instead, allowing the SSE implementations to stay on the simd unit.

I can't find any cases where vector AND/OR operations use custom lowering, but if I have missed something it would be possible to add a TLI::isOperationLegalOrCustomOrPromote function to cover all cases - what do you think?

Repository:
  rL LLVM

http://reviews.llvm.org/D19805

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  test/CodeGen/X86/vector-bitreverse.ll

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