[PATCH] D19410: [scan-build] fix logic error warnings emitted on llvm code base

[Apelete Seketeli via llvm-commits]

apelete updated this revision to Diff 54867.
apelete added a comment.

[scan-build] fix logic error warnings emitted on llvm code base

Changes since last revision:

- check TargetRegisterClass variable value after MachineOperand initialization and return based on the kind of MachineOperand.


http://reviews.llvm.org/D19410

Files:
  lib/Analysis/ScalarEvolution.cpp
  lib/IR/Verifier.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -9961,7 +9961,9 @@
     return true;
 
   // '.align' is target specifically handled to mean 2**2 byte alignment.
-  if (getStreamer().getCurrentSection().first->UseCodeAlign())
+  const MCSection *Section = getStreamer().getCurrentSection().first;
+  assert(Section && "must have section to emit alignment");
+  if (Section->UseCodeAlign())
     getStreamer().EmitCodeAlignment(4, 0);
   else
     getStreamer().EmitValueToAlignment(4, 0, 1, 0);
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1833,9 +1833,15 @@
   const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
   const TargetRegisterClass *DefinedRC =
       OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
+
   if (!MO)
     MO = &MI->getOperand(OpIdx);
 
+  if (!DefinedRC) {
+    // This operand expects an immediate.
+    return !MO->isReg();
+  }
+
   if (isVALU(*MI) &&
       usesConstantBus(MRI, *MO, DefinedRC->getSize())) {
 
@@ -1860,15 +1866,9 @@
     return isLegalRegOperand(MRI, OpInfo, *MO);
   }
 
-
   // Handle non-register types that are treated like immediates.
   assert(MO->isImm() || MO->isTargetIndex() || MO->isFI());
 
-  if (!DefinedRC) {
-    // This operand expects an immediate.
-    return true;
-  }
-
   return isImmOperandLegal(MI, OpIdx, *MO);
 }
 
Index: lib/IR/Verifier.cpp
===================================================================
--- lib/IR/Verifier.cpp
+++ lib/IR/Verifier.cpp
@@ -2020,7 +2020,7 @@
         continue;
 
       // FIXME: Once N is canonical, check "SP == &N".
-      Assert(SP->describes(&F),
+      Assert(SP && SP->describes(&F),
              "!dbg attachment points at wrong subprogram for function", N, &F,
              &I, DL, Scope, SP);
     }
Index: lib/Analysis/ScalarEvolution.cpp
===================================================================
--- lib/Analysis/ScalarEvolution.cpp
+++ lib/Analysis/ScalarEvolution.cpp
@@ -5554,6 +5554,8 @@
   if (NumExits == 1)
     return;
 
+  assert(ENT && "ExitNotTakenExtras array is NULL, cannot further compute exits");
+
   auto &Exits = ExitNotTaken.ExtraInfo->Exits;
 
   // Handle the rare case of multiple computable exits.


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