[PATCH] D19150: [mips][microMIPS] Implement LL, SC, LWM32, SWM32, MOVEP, ROTR, ROTRV and SYSCALL instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 15 03:12:30 PDT 2016
sdardis requested changes to this revision.
sdardis added a reviewer: sdardis.
sdardis added a comment.
This revision now requires changes to proceed.
Minor nits. When adding to the */(in)valid.s test files can you integrate the new instructions in alphabetical order with existing instructions? Also, group instructions of a similar size.
I know the files themselves aren't wholly consistent with this, so it doesn't have to be perfect.
================
Comment at: lib/Target/Mips/Mips32r6InstrInfo.td:792-799
@@ -789,10 +791,10 @@
def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
+ def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
}
-def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
}
def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
----------------
Join these blocks together.
================
Comment at: test/MC/Disassembler/Mips/micromips32r6/valid.txt:279-289
@@ -278,1 +278,12 @@
0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16
+0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
+0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
+0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
+0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
+0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
+0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x00 0x42 0x38 0xc0 # CHECK: rotr $2, $2, 7
+0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
+0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
+0x00 0x00 0x8b 0x7c # CHECK: syscall
+0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
----------------
As these are not ASE or floating point specific microMIPS instructions, can you place them between lines 31-100 in alphabetical order? It's more consistent that way.
The movep should be placed in one of the 16 bit instruction blocks.
================
Comment at: test/MC/Disassembler/Mips/micromips64r6/valid.txt:218-228
@@ -217,1 +217,12 @@
0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5
+0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
+0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
+0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
+0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
+0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
+0x84 0x34 # CHECK: movep $5, $6, $2, $3
+0x00 0x42 0x38 0xc0 # CHECK: rotr $2, $2, 7
+0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
+0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
+0x00 0x00 0x8b 0x7c # CHECK: syscall
+0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
----------------
Here too, just place these instructions with the 32bit instructions? move should be with the 16bit instructions.
================
Comment at: test/MC/Mips/micromips32r6/invalid.s:136
@@ +135,2 @@
+ rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
+ rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
----------------
Can you add rotrv with an immediate operand here, syscall with a register operand, syscall with an out of range immediate? Finally please place the instructions in alphabetical order with the existing instructions depending on whether their are 32bit or 16bit long.
================
Comment at: test/MC/Mips/micromips32r6/valid.s:278-299
@@ -277,1 +277,23 @@
mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c]
+ ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08]
+ sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08]
+ lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08]
+ lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08]
+ lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08]
+ lwm32 $16, $17, $ra, 64($sp) # CHECK: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40]
+ lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+ lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
+ swm32 $16, $17, 8($4) # CHECK: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08]
+ swm32 $16, $17, 8($sp) # CHECK: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08]
+ swm32 $16, $17, $ra, 8($4) # CHECK: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08]
+ swm32 $16, $17, $ra, 64($sp) # CHECK: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40]
+ swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
+ movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
+ rotr $2, 7 # CHECK: rotr $2, $2, 7 # encoding: [0x00,0x42,0x38,0xc0]
+ rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0]
+ rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
+ syscall # CHECK: syscall # encoding: [0x00,0x00,0x8b,0x7c]
+ syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
----------------
Try to integrate these into the first 100~ lines alphabetically.
http://reviews.llvm.org/D19150
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