[PATCH] D18890: [AArch64] add SSA Load Store optimization pass

[Jongwon Lee via llvm-commits]

JongwonLee marked an inline comment as done.

================
Comment at: lib/Target/AArch64/AArch64SSALoadStoreOptimizer.cpp:414-421
@@ +413,10 @@
+  //    changed.
+  //     e.g.,
+  //     %vreg2 = LDURWi %vreg0, -76;
+  //     %vreg3 = LDURWi %vreg0, -72;
+  //     STURWi %vreg2, %vreg1, -44;
+  //     STURWi %vreg3, %vreg1, -40;
+  //     ; becomes
+  //     %vreg2 = LDURXi %vreg0, -76;
+  //     STURXi %vreg2, %vreg1, -44;
+  //
----------------
junbuml wrote:
> I see your point. In that case why don't you change like :
>   reg2 = wide-load [mem1]
>   wide-store reg2, [mem2]
```
reg2 = load [mem1]
reg1 = load [mem1 +4]
```
The above two loads can be the below one load.
```
reg2 = wide-laod [mem1]
```

```
store reg1, [mem2]
store reg2, [mem2 +4]
```
But, the above two stores cannot be the below one store.

```
wide-store reg2, [mem2]
```
The correct form of wide-store should have reg1 as its source operand.

```
wide-store reg1, [mem2]
```


================
Comment at: lib/Target/AArch64/AArch64SSALoadStoreOptimizer.cpp:425
@@ +424,3 @@
+  //    the original value.
+  //     e.g.,
+  //     %vreg2 = LDRWui %vreg0, 4;
----------------
junbuml wrote:
> In order to merge the second load / store to the first load / store,  we need to make sure that there is no memory operations aliasing with the second one. For example, in the code below, there is a store between the loads. In this case we cannot move the second load to the first without knowing that mem1 and mem3 is not pointing the same address.
> 
>   reg1 = load [mem1]
>   store reg3, [mem3 + 4]
>   reg2 = load [mem1 +4]
>   
>   store reg1, [mem2]
>   store reg2, [mem2 + 4]
> 
> 
Thanks. You are right. I fixed the code to consider all the aliases between two loads and between two stores.


http://reviews.llvm.org/D18890