[PATCH] D18890: [AArch64] add SSA Load Store optimization pass

[Jun Bum Lim via llvm-commits]

junbuml added inline comments.

================
Comment at: lib/Target/AArch64/AArch64SSALoadStoreOptimizer.cpp:33
@@ +32,3 @@
+#define MAX_UNSCALED_OFFSET 255
+#define MIN_UNSCALED_OFFSET 256
+
----------------
-256

================
Comment at: lib/Target/AArch64/AArch64SSALoadStoreOptimizer.cpp:111-114
@@ +110,6 @@
+
+  if (AA->alias(LocA, LocB))
+    return true;
+
+  return false;
+}
----------------
return AA->alias(LocA, LocB);

================
Comment at: lib/Target/AArch64/AArch64SSALoadStoreOptimizer.cpp:414-421
@@ +413,10 @@
+  //    changed.
+  //     e.g.,
+  //     %vreg2 = LDURWi %vreg0, -76;
+  //     %vreg3 = LDURWi %vreg0, -72;
+  //     STURWi %vreg2, %vreg1, -44;
+  //     STURWi %vreg3, %vreg1, -40;
+  //     ; becomes
+  //     %vreg2 = LDURXi %vreg0, -76;
+  //     STURXi %vreg2, %vreg1, -44;
+  //
----------------
I see your point. In that case why don't you change like :
  reg2 = wide-load [mem1]
  wide-store reg2, [mem2]

================
Comment at: lib/Target/AArch64/AArch64SSALoadStoreOptimizer.cpp:425
@@ +424,3 @@
+  //    the original value.
+  //     e.g.,
+  //     %vreg2 = LDRWui %vreg0, 4;
----------------
In order to merge the second load / store to the first load / store,  we need to make sure that there is no memory operations aliasing with the second one. For example, in the code below, there is a store between the loads. In this case we cannot move the second load to the first without knowing that mem1 and mem3 is not pointing the same address.

  reg1 = load [mem1]
  store reg3, [mem3 + 4]
  reg2 = load [mem1 +4]
  
  store reg1, [mem2]
  store reg2, [mem2 + 4]




http://reviews.llvm.org/D18890