[PATCH] D18890: [AArch64] add SSA Load Store optimization pass

[Jongwon Lee via llvm-commits]

JongwonLee added a comment.

In http://reviews.llvm.org/D18890#397239, @mcrosier wrote:

> In http://reviews.llvm.org/D18890#396878, @rengolin wrote:
>
> > Some good changes, some comments, but I still wonder why:
> >
> > 1. You haven't done this in the already existing LdStOpt pass.
>
>
> I imagine one benefit of merging the 32 bit loads/stores before register allocation is that it saves a register, right?
>
>   ldr w2, [x0]
>   ldr w3, [x0, #4]
>   str w2, [x1]
>   str w3, [x1, #4]
>   
>
> becomes
>
>   ldr x2, [x0]
>   str x2, [x1]
>   
>
> saving x3.


Right. And we also get the smaller code size.


================
Comment at: test/CodeGen/AArch64/ssa-ldst-opt.ll:9-13
@@ +8,7 @@
+  %ld.ptr1 = getelementptr i32, i32* %p1, i64 -19
+  %1 = load i32, i32* %ld.ptr1, align 4
+  %st.ptr1 = getelementptr i32, i32* %p2, i64 -11
+  store i32 %1, i32* %st.ptr1, align 4
+  %ld.ptr2 = getelementptr i32, i32* %p1, i64 -18
+  %2 = load i32, i32* %ld.ptr2, align 4
+  %st.ptr2 = getelementptr i32, i32* %p2, i64 -10
----------------
junbuml wrote:
> Merging the second load to the first load seems to be wrong without alias check between the second load and the first store.
Thanks. I missed this case. In the test code, metadata for tbaa is added. In the source code,the routine for checking alias is added.


http://reviews.llvm.org/D18890