[PATCH] D18890: [AArch64] add SSA Load Store optimization pass

[Chad Rosier via llvm-commits]

mcrosier added a comment.

In http://reviews.llvm.org/D18890#396878, @rengolin wrote:

> Some good changes, some comments, but I still wonder why:
>
> 1. You haven't done this in the already existing LdStOpt pass.


I imagine one benefit of merging the 32 bit loads/stores before register allocation is that is saves a register, right?

  ldr w2, [x0]
  ldr w3, [x0, #4]
  str w2, [x1]
  str w3, [x1, #4]

becomes

  ldr x2, [x0]
  str x2, [x1]

right?


http://reviews.llvm.org/D18890