[PATCH] D14840: [X86] Detect SAD patterns and emit psadbw instructions on X86.
Ahmed Bougacha via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 29 09:51:25 PDT 2016
ab added a comment.
So, I understand the huge tests are required to trigger the reduction recognizer. Have you considered changing that, for the sake of testability? The most obvious thing I can think of is to represent the flag as metadata in IR. That has other benefits:
- do the analysis in IR rather than in SelectionDAGBuilder, which is already a big enough mess as it is ;)
- only do the analysis for targets that use it: if only X86 can select reduction ops, what's the point in recognizing them elsewhere?
Another (possibly even crappier) alternative: add some "stress-test" commandline flag that overrides the isVectorReduction check on ADDs (or even adds the flag everywhere).
http://reviews.llvm.org/D14840
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