[PATCH] D18492: [X86][SSE] Vectorize a bit (AND/XOR/OR) op if a BUILD_VECTOR has the same op for all their scalar elements.

[Chandler Carruth via llvm-commits]

chandlerc accepted this revision.
chandlerc added a comment.
This revision is now accepted and ready to land.

Looks good with a minor adjustment below.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:6654-6670
@@ +6653,19 @@
+      return SDValue();
+
+    SmallVector<SDValue, 4> LHSElts, RHSElts;
+    for (SDValue Elt : Op->ops()) {
+      SDValue LHS = Elt.getOperand(0);
+      SDValue RHS = Elt.getOperand(1);
+
+      // We expect the canonicalized RHS operand to be the constant.
+      if (!isa<ConstantSDNode>(RHS))
+        return SDValue();
+      LHSElts.push_back(LHS);
+      RHSElts.push_back(RHS);
+    }
+
+    SDValue LHS = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, LHSElts);
+    SDValue RHS = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, RHSElts);
+    return DAG.getNode(Opcode, DL, VT, LHS, RHS);
+  }
+  }
----------------
I would 'break' from the 3 cases you accept, and add a default that bails out. That will allow you to early-exit and reduce indentation for the entire block here.


Repository:
  rL LLVM

http://reviews.llvm.org/D18492