[PATCH] D18148: [mips] Range check simm10

[Daniel Sanders via llvm-commits]

dsanders added inline comments.

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Comment at: test/MC/Mips/mips64r2/invalid.s:65-70
@@ -64,4 +64,8 @@
         pref 32, 255($7)     # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+        seqi $2, $3, -1025   # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
+        seqi $2, $3, 1024    # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
         sll $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
         sll $2, $3, 32       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
+        snei $2, $3, -1025   # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
+        snei $2, $3, 1024    # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
         srl $2, $3, -1       # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
----------------
vkalintiris wrote:
> These new instructions are Octeon-specific but the assembler doesn't report any error. Shouldn't we add them in MC/Mips/cnmips/invalid.s, instead?
> These new instructions are Octeon-specific ...

Well spotted. I've posted another patch to make this much more obvious and fix a few PredicateControl usage mistakes at the same time.

> ... but the assembler doesn't report any error.

This is because we can only report one error and the out-of-range immediate has priority. If the immediate were in range then it would have emitted an error about the lack of cnMIPS.

> Shouldn't we add them in MC/Mips/cnmips/invalid.s, instead?

I agree. I'll post an updated patch shortly.


http://reviews.llvm.org/D18148