[PATCH] D18148: [mips] Range check simm10
Vasileios Kalintiris via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 21 07:48:08 PDT 2016
vkalintiris added inline comments.
================
Comment at: test/MC/Mips/mips64r2/invalid.s:65-70
@@ -64,4 +64,8 @@
pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate
+ seqi $2, $3, -1025 # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
+ seqi $2, $3, 1024 # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
sll $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
+ snei $2, $3, -1025 # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
+ snei $2, $3, 1024 # CHECK: :[[@LINE]]:22: error: expected 10-bit signed immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate
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These new instructions are Octeon-specific but the assembler doesn't report any error. Shouldn't we add them in MC/Mips/cnmips/invalid.s, instead?
http://reviews.llvm.org/D18148
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