[llvm] r263303 - [X86][SSE] Simplify vector LOAD + EXTEND on pre-SSE41 hardware
Eric Christopher via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 14 15:31:58 PDT 2016
Hi Simon,
I'm seeing asserts with this and halide on x86. I'm working with Alina to
get a testcase for you, but would you mind terribly if we reverted this in
the meantime?
-eric
On Fri, Mar 11, 2016 at 2:22 PM Simon Pilgrim via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: rksimon
> Date: Fri Mar 11 16:18:05 2016
> New Revision: 263303
>
> URL: http://llvm.org/viewvc/llvm-project?rev=263303&view=rev
> Log:
> [X86][SSE] Simplify vector LOAD + EXTEND on pre-SSE41 hardware
>
> Improve vector extension of vectors on hardware without dedicated
> VSEXT/VZEXT instructions.
>
> We already convert these to
> SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG but can further improve
> this by using the legalizer instead of prematurely splitting into legal
> vectors in the combine as this only properly helps for lowering to
> VSEXT/VZEXT.
>
> Removes a lot of unnecessary any_extend + mask pattern - (Fix for PR25718).
>
> Differential Revision: http://reviews.llvm.org/D17932
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> llvm/trunk/test/CodeGen/X86/vector-zext.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=263303&r1=263302&r2=263303&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Mar 11
> 16:18:05 2016
> @@ -653,6 +653,7 @@ private:
> void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
> + void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi);
>
> void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
> void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=263303&r1=263302&r2=263303&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Mar 11
> 16:18:05 2016
> @@ -621,6 +621,12 @@ void DAGTypeLegalizer::SplitVectorResult
> SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
> break;
>
> + case ISD::ANY_EXTEND_VECTOR_INREG:
> + case ISD::SIGN_EXTEND_VECTOR_INREG:
> + case ISD::ZERO_EXTEND_VECTOR_INREG:
> + SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
> + break;
> +
> case ISD::BITREVERSE:
> case ISD::BSWAP:
> case ISD::CONVERT_RNDSAT:
> @@ -917,6 +923,39 @@ void DAGTypeLegalizer::SplitVecRes_Inreg
> DAG.getValueType(HiVT));
> }
>
> +void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
> + SDValue &Hi) {
> + unsigned Opcode = N->getOpcode();
> + SDValue N0 = N->getOperand(0);
> +
> + SDLoc dl(N);
> + SDValue InLo, InHi;
> + GetSplitVector(N0, InLo, InHi);
> + EVT InLoVT = InLo.getValueType();
> + unsigned InNumElements = InLoVT.getVectorNumElements();
> +
> + EVT OutLoVT, OutHiVT;
> + std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
> + unsigned OutNumElements = OutLoVT.getVectorNumElements();
> + assert((2 * OutNumElements) <= InNumElements &&
> + "Illegal extend vector in reg split");
> +
> + // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
> + // input vector (i.e. we only use InLo):
> + // OutLo will extend the first OutNumElements from InLo.
> + // OutHi will extend the next OutNumElements from InLo.
> +
> + // Shuffle the elements from InLo for OutHi into the bottom elements to
> + // create a 'fake' InHi.
> + SmallVector<int, 8> SplitHi(InNumElements, -1);
> + for (unsigned i = 0; i != OutNumElements; ++i)
> + SplitHi[i] = i + OutNumElements;
> + InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT),
> SplitHi);
> +
> + Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
> + Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
> +}
> +
> void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue
> &Lo,
> SDValue &Hi) {
> SDValue Vec = N->getOperand(0);
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=263303&r1=263302&r2=263303&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Mar 11 16:18:05 2016
> @@ -28534,7 +28534,9 @@ static SDValue combineToExtendVectorInRe
>
> // If target-size is 128-bits (or 256-bits on AVX2 target), then
> convert to
> // ISD::*_EXTEND_VECTOR_INREG which ensures lowering to X86ISD::V*EXT.
> - if (VT.is128BitVector() || (VT.is256BitVector() &&
> Subtarget.hasInt256())) {
> + // Also use this if we don't have SSE41 to allow the legalizer do its
> job.
> + if (!Subtarget.hasSSE41() || VT.is128BitVector() ||
> + (VT.is256BitVector() && Subtarget.hasInt256())) {
> SDValue ExOp = ExtendVecSize(DL, N0, VT.getSizeInBits());
> return Opcode == ISD::SIGN_EXTEND
> ? DAG.getSignExtendVectorInReg(ExOp, DL, VT)
>
> Modified: llvm/trunk/test/CodeGen/X86/vector-zext.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-zext.ll?rev=263303&r1=263302&r2=263303&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/vector-zext.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/vector-zext.ll Fri Mar 11 16:18:05 2016
> @@ -544,23 +544,20 @@ define <4 x i64> @load_zext_4i8_to_4i64(
> ; SSE2-LABEL: load_zext_4i8_to_4i64:
> ; SSE2: # BB#0: # %entry
> ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
> -; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
> -; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
> -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
> -; SSE2-NEXT: movdqa {{.*#+}} xmm2 =
> [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
> -; SSE2-NEXT: pand %xmm2, %xmm0
> -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
> -; SSE2-NEXT: pand %xmm2, %xmm1
> +; SSE2-NEXT: pxor %xmm2, %xmm2
> +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
> +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
> +; SSE2-NEXT: movdqa %xmm1, %xmm0
> +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
> +; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
> ; SSE2-NEXT: retq
> ;
> ; SSSE3-LABEL: load_zext_4i8_to_4i64:
> ; SSSE3: # BB#0: # %entry
> ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
> -; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
> -; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
> ; SSSE3-NEXT: movdqa %xmm1, %xmm0
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm0 =
> xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[4],zero,zero,zero,zero,zero,zero,zero
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm1 =
> xmm1[8],zero,zero,zero,zero,zero,zero,zero,xmm1[12],zero,zero,zero,zero,zero,zero,zero
> +; SSSE3-NEXT: pshufb {{.*#+}} xmm0 =
> xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
> +; SSSE3-NEXT: pshufb {{.*#+}} xmm1 =
> xmm1[2],zero,zero,zero,zero,zero,zero,zero,xmm1[3],zero,zero,zero,zero,zero,zero,zero
> ; SSSE3-NEXT: retq
> ;
> ; SSE41-LABEL: load_zext_4i8_to_4i64:
> @@ -625,22 +622,21 @@ define <8 x i32> @load_zext_8i8_to_8i32(
> ; SSE2-LABEL: load_zext_8i8_to_8i32:
> ; SSE2: # BB#0: # %entry
> ; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
> -; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
> +; SSE2-NEXT: pxor %xmm2, %xmm2
> +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
> ; SSE2-NEXT: movdqa %xmm1, %xmm0
> -; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
> -; SSE2-NEXT: movdqa {{.*#+}} xmm2 =
> [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
> -; SSE2-NEXT: pand %xmm2, %xmm0
> -; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 =
> xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
> -; SSE2-NEXT: pand %xmm2, %xmm1
> +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 =
> xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
> +; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 =
> xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
> ; SSE2-NEXT: retq
> ;
> ; SSSE3-LABEL: load_zext_8i8_to_8i32:
> ; SSSE3: # BB#0: # %entry
> ; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
> -; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
> +; SSSE3-NEXT: pxor %xmm2, %xmm2
> +; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
> ; SSSE3-NEXT: movdqa %xmm1, %xmm0
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm0 =
> xmm0[0],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[6],zero,zero,zero
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm1 =
> xmm1[8],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[14],zero,zero,zero
> +; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 =
> xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
> +; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 =
> xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
> ; SSSE3-NEXT: retq
> ;
> ; SSE41-LABEL: load_zext_8i8_to_8i32:
> @@ -674,34 +670,33 @@ entry:
> define <8 x i64> @load_zext_8i8_to_8i64(<8 x i8> *%ptr) {
> ; SSE2-LABEL: load_zext_8i8_to_8i64:
> ; SSE2: # BB#0: # %entry
> -; SSE2-NEXT: movq {{.*#+}} xmm3 = mem[0],zero
> -; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 =
> xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
> -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,1,0,3]
> -; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]
> -; SSE2-NEXT: movdqa {{.*#+}} xmm4 =
> [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
> -; SSE2-NEXT: pand %xmm4, %xmm0
> -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,1,3]
> -; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,5,6,7]
> -; SSE2-NEXT: pand %xmm4, %xmm1
> -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,1,2,3]
> -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,5,6,7]
> -; SSE2-NEXT: pand %xmm4, %xmm2
> -; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[3,1,3,3]
> -; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,5,6,7]
> -; SSE2-NEXT: pand %xmm4, %xmm3
> +; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
> +; SSE2-NEXT: pxor %xmm4, %xmm4
> +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3]
> +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 =
> xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
> +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
> +; SSE2-NEXT: movdqa %xmm1, %xmm0
> +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
> +; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]
> +; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 =
> xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3],xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
> +; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 =
> xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
> +; SSE2-NEXT: movdqa %xmm3, %xmm2
> +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
> +; SSE2-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]
> ; SSE2-NEXT: retq
> ;
> ; SSSE3-LABEL: load_zext_8i8_to_8i64:
> ; SSSE3: # BB#0: # %entry
> -; SSSE3-NEXT: movq {{.*#+}} xmm3 = mem[0],zero
> -; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 =
> xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
> -; SSSE3-NEXT: movdqa %xmm3, %xmm0
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm0 =
> xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero
> -; SSSE3-NEXT: movdqa %xmm3, %xmm1
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm1 =
> xmm1[4],zero,zero,zero,zero,zero,zero,zero,xmm1[6],zero,zero,zero,zero,zero,zero,zero
> +; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
> +; SSSE3-NEXT: movdqa {{.*#+}} xmm4 =
> [0,128,128,128,128,128,128,128,1,128,128,128,128,128,128,128]
> +; SSSE3-NEXT: movdqa %xmm1, %xmm0
> +; SSSE3-NEXT: pshufb %xmm4, %xmm0
> +; SSSE3-NEXT: movdqa {{.*#+}} xmm5 =
> [2,128,128,128,128,128,128,128,3,128,128,128,128,128,128,128]
> +; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3]
> +; SSSE3-NEXT: pshufb %xmm5, %xmm1
> ; SSSE3-NEXT: movdqa %xmm3, %xmm2
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm2 =
> xmm2[8],zero,zero,zero,zero,zero,zero,zero,xmm2[10],zero,zero,zero,zero,zero,zero,zero
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm3 =
> xmm3[12],zero,zero,zero,zero,zero,zero,zero,xmm3[14],zero,zero,zero,zero,zero,zero,zero
> +; SSSE3-NEXT: pshufb %xmm4, %xmm2
> +; SSSE3-NEXT: pshufb %xmm5, %xmm3
> ; SSSE3-NEXT: retq
> ;
> ; SSE41-LABEL: load_zext_8i8_to_8i64:
> @@ -851,21 +846,21 @@ define <4 x i64> @load_zext_4i16_to_4i64
> ; SSE2-LABEL: load_zext_4i16_to_4i64:
> ; SSE2: # BB#0: # %entry
> ; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
> -; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
> -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
> -; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0,65535,0,0,0]
> -; SSE2-NEXT: pand %xmm2, %xmm0
> -; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
> -; SSE2-NEXT: pand %xmm2, %xmm1
> +; SSE2-NEXT: pxor %xmm2, %xmm2
> +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
> +; SSE2-NEXT: movdqa %xmm1, %xmm0
> +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
> +; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
> ; SSE2-NEXT: retq
> ;
> ; SSSE3-LABEL: load_zext_4i16_to_4i64:
> ; SSSE3: # BB#0: # %entry
> ; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
> -; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
> +; SSSE3-NEXT: pxor %xmm2, %xmm2
> +; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 =
> xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
> ; SSSE3-NEXT: movdqa %xmm1, %xmm0
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm0 =
> xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[4,5],zero,zero,zero,zero,zero,zero
> -; SSSE3-NEXT: pshufb {{.*#+}} xmm1 =
> xmm1[8,9],zero,zero,zero,zero,zero,zero,xmm1[12,13],zero,zero,zero,zero,zero,zero
> +; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
> +; SSSE3-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
> ; SSSE3-NEXT: retq
> ;
> ; SSE41-LABEL: load_zext_4i16_to_4i64:
>
>
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