<div dir="ltr">Hi Simon,<div><br></div><div>I'm seeing asserts with this and halide on x86. I'm working with Alina to get a testcase for you, but would you mind terribly if we reverted this in the meantime?</div><div><br></div><div>-eric</div><br><div class="gmail_quote"><div dir="ltr">On Fri, Mar 11, 2016 at 2:22 PM Simon Pilgrim via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Fri Mar 11 16:18:05 2016<br>
New Revision: 263303<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=263303&view=rev" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=263303&view=rev</a><br>
Log:<br>
[X86][SSE] Simplify vector LOAD + EXTEND on pre-SSE41 hardware<br>
<br>
Improve vector extension of vectors on hardware without dedicated VSEXT/VZEXT instructions.<br>
<br>
We already convert these to SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG but can further improve this by using the legalizer instead of prematurely splitting into legal vectors in the combine as this only properly helps for lowering to VSEXT/VZEXT.<br>
<br>
Removes a lot of unnecessary any_extend + mask pattern - (Fix for PR25718).<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D17932" rel="noreferrer" target="_blank">http://reviews.llvm.org/D17932</a><br>
<br>
Modified:<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/vector-zext.ll<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=263303&r1=263302&r2=263303&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=263303&r1=263302&r2=263303&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Mar 11 16:18:05 2016<br>
@@ -653,6 +653,7 @@ private:<br>
void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);<br>
void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);<br>
void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);<br>
+ void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi);<br>
<br>
void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);<br>
void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=263303&r1=263302&r2=263303&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=263303&r1=263302&r2=263303&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Mar 11 16:18:05 2016<br>
@@ -621,6 +621,12 @@ void DAGTypeLegalizer::SplitVectorResult<br>
SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);<br>
break;<br>
<br>
+ case ISD::ANY_EXTEND_VECTOR_INREG:<br>
+ case ISD::SIGN_EXTEND_VECTOR_INREG:<br>
+ case ISD::ZERO_EXTEND_VECTOR_INREG:<br>
+ SplitVecRes_ExtVecInRegOp(N, Lo, Hi);<br>
+ break;<br>
+<br>
case ISD::BITREVERSE:<br>
case ISD::BSWAP:<br>
case ISD::CONVERT_RNDSAT:<br>
@@ -917,6 +923,39 @@ void DAGTypeLegalizer::SplitVecRes_Inreg<br>
DAG.getValueType(HiVT));<br>
}<br>
<br>
+void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,<br>
+ SDValue &Hi) {<br>
+ unsigned Opcode = N->getOpcode();<br>
+ SDValue N0 = N->getOperand(0);<br>
+<br>
+ SDLoc dl(N);<br>
+ SDValue InLo, InHi;<br>
+ GetSplitVector(N0, InLo, InHi);<br>
+ EVT InLoVT = InLo.getValueType();<br>
+ unsigned InNumElements = InLoVT.getVectorNumElements();<br>
+<br>
+ EVT OutLoVT, OutHiVT;<br>
+ std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));<br>
+ unsigned OutNumElements = OutLoVT.getVectorNumElements();<br>
+ assert((2 * OutNumElements) <= InNumElements &&<br>
+ "Illegal extend vector in reg split");<br>
+<br>
+ // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the<br>
+ // input vector (i.e. we only use InLo):<br>
+ // OutLo will extend the first OutNumElements from InLo.<br>
+ // OutHi will extend the next OutNumElements from InLo.<br>
+<br>
+ // Shuffle the elements from InLo for OutHi into the bottom elements to<br>
+ // create a 'fake' InHi.<br>
+ SmallVector<int, 8> SplitHi(InNumElements, -1);<br>
+ for (unsigned i = 0; i != OutNumElements; ++i)<br>
+ SplitHi[i] = i + OutNumElements;<br>
+ InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);<br>
+<br>
+ Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);<br>
+ Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);<br>
+}<br>
+<br>
void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,<br>
SDValue &Hi) {<br>
SDValue Vec = N->getOperand(0);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=263303&r1=263302&r2=263303&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=263303&r1=263302&r2=263303&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Mar 11 16:18:05 2016<br>
@@ -28534,7 +28534,9 @@ static SDValue combineToExtendVectorInRe<br>
<br>
// If target-size is 128-bits (or 256-bits on AVX2 target), then convert to<br>
// ISD::*_EXTEND_VECTOR_INREG which ensures lowering to X86ISD::V*EXT.<br>
- if (VT.is128BitVector() || (VT.is256BitVector() && Subtarget.hasInt256())) {<br>
+ // Also use this if we don't have SSE41 to allow the legalizer do its job.<br>
+ if (!Subtarget.hasSSE41() || VT.is128BitVector() ||<br>
+ (VT.is256BitVector() && Subtarget.hasInt256())) {<br>
SDValue ExOp = ExtendVecSize(DL, N0, VT.getSizeInBits());<br>
return Opcode == ISD::SIGN_EXTEND<br>
? DAG.getSignExtendVectorInReg(ExOp, DL, VT)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vector-zext.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-zext.ll?rev=263303&r1=263302&r2=263303&view=diff" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-zext.ll?rev=263303&r1=263302&r2=263303&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vector-zext.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vector-zext.ll Fri Mar 11 16:18:05 2016<br>
@@ -544,23 +544,20 @@ define <4 x i64> @load_zext_4i8_to_4i64(<br>
; SSE2-LABEL: load_zext_4i8_to_4i64:<br>
; SSE2: # BB#0: # %entry<br>
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]<br>
-; SSE2-NEXT: pand %xmm2, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]<br>
-; SSE2-NEXT: pand %xmm2, %xmm1<br>
+; SSE2-NEXT: pxor %xmm2, %xmm2<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
+; SSE2-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]<br>
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: load_zext_4i8_to_4i64:<br>
; SSSE3: # BB#0: # %entry<br>
; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]<br>
; SSSE3-NEXT: movdqa %xmm1, %xmm0<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[4],zero,zero,zero,zero,zero,zero,zero<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[8],zero,zero,zero,zero,zero,zero,zero,xmm1[12],zero,zero,zero,zero,zero,zero,zero<br>
+; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero<br>
+; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[2],zero,zero,zero,zero,zero,zero,zero,xmm1[3],zero,zero,zero,zero,zero,zero,zero<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: load_zext_4i8_to_4i64:<br>
@@ -625,22 +622,21 @@ define <8 x i32> @load_zext_8i8_to_8i32(<br>
; SSE2-LABEL: load_zext_8i8_to_8i32:<br>
; SSE2: # BB#0: # %entry<br>
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>
+; SSE2-NEXT: pxor %xmm2, %xmm2<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]<br>
; SSE2-NEXT: movdqa %xmm1, %xmm0<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]<br>
-; SSE2-NEXT: pand %xmm2, %xmm0<br>
-; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>
-; SSE2-NEXT: pand %xmm2, %xmm1<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]<br>
+; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: load_zext_8i8_to_8i32:<br>
; SSSE3: # BB#0: # %entry<br>
; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]<br>
+; SSSE3-NEXT: pxor %xmm2, %xmm2<br>
+; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]<br>
; SSSE3-NEXT: movdqa %xmm1, %xmm0<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[6],zero,zero,zero<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[8],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[14],zero,zero,zero<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]<br>
+; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: load_zext_8i8_to_8i32:<br>
@@ -674,34 +670,33 @@ entry:<br>
define <8 x i64> @load_zext_8i8_to_8i64(<8 x i8> *%ptr) {<br>
; SSE2-LABEL: load_zext_8i8_to_8i64:<br>
; SSE2: # BB#0: # %entry<br>
-; SSE2-NEXT: movq {{.*#+}} xmm3 = mem[0],zero<br>
-; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,1,0,3]<br>
-; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]<br>
-; SSE2-NEXT: pand %xmm4, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,1,3]<br>
-; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,5,6,7]<br>
-; SSE2-NEXT: pand %xmm4, %xmm1<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,1,2,3]<br>
-; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,5,6,7]<br>
-; SSE2-NEXT: pand %xmm4, %xmm2<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[3,1,3,3]<br>
-; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,5,6,7]<br>
-; SSE2-NEXT: pand %xmm4, %xmm3<br>
+; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero<br>
+; SSE2-NEXT: pxor %xmm4, %xmm4<br>
+; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]<br>
+; SSE2-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]<br>
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]<br>
+; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3],xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]<br>
+; SSE2-NEXT: movdqa %xmm3, %xmm2<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]<br>
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: load_zext_8i8_to_8i64:<br>
; SSSE3: # BB#0: # %entry<br>
-; SSSE3-NEXT: movq {{.*#+}} xmm3 = mem[0],zero<br>
-; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]<br>
-; SSSE3-NEXT: movdqa %xmm3, %xmm0<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero<br>
-; SSSE3-NEXT: movdqa %xmm3, %xmm1<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[4],zero,zero,zero,zero,zero,zero,zero,xmm1[6],zero,zero,zero,zero,zero,zero,zero<br>
+; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero<br>
+; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [0,128,128,128,128,128,128,128,1,128,128,128,128,128,128,128]<br>
+; SSSE3-NEXT: movdqa %xmm1, %xmm0<br>
+; SSSE3-NEXT: pshufb %xmm4, %xmm0<br>
+; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2,128,128,128,128,128,128,128,3,128,128,128,128,128,128,128]<br>
+; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3]<br>
+; SSSE3-NEXT: pshufb %xmm5, %xmm1<br>
; SSSE3-NEXT: movdqa %xmm3, %xmm2<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm2 = xmm2[8],zero,zero,zero,zero,zero,zero,zero,xmm2[10],zero,zero,zero,zero,zero,zero,zero<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm3 = xmm3[12],zero,zero,zero,zero,zero,zero,zero,xmm3[14],zero,zero,zero,zero,zero,zero,zero<br>
+; SSSE3-NEXT: pshufb %xmm4, %xmm2<br>
+; SSSE3-NEXT: pshufb %xmm5, %xmm3<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: load_zext_8i8_to_8i64:<br>
@@ -851,21 +846,21 @@ define <4 x i64> @load_zext_4i16_to_4i64<br>
; SSE2-LABEL: load_zext_4i16_to_4i64:<br>
; SSE2: # BB#0: # %entry<br>
; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero<br>
-; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]<br>
-; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0,65535,0,0,0]<br>
-; SSE2-NEXT: pand %xmm2, %xmm0<br>
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]<br>
-; SSE2-NEXT: pand %xmm2, %xmm1<br>
+; SSE2-NEXT: pxor %xmm2, %xmm2<br>
+; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
+; SSE2-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]<br>
+; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
; SSE2-NEXT: retq<br>
;<br>
; SSSE3-LABEL: load_zext_4i16_to_4i64:<br>
; SSSE3: # BB#0: # %entry<br>
; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero<br>
-; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]<br>
+; SSSE3-NEXT: pxor %xmm2, %xmm2<br>
+; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
; SSSE3-NEXT: movdqa %xmm1, %xmm0<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[4,5],zero,zero,zero,zero,zero,zero<br>
-; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[8,9],zero,zero,zero,zero,zero,zero,xmm1[12,13],zero,zero,zero,zero,zero,zero<br>
+; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]<br>
+; SSSE3-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]<br>
; SSSE3-NEXT: retq<br>
;<br>
; SSE41-LABEL: load_zext_4i16_to_4i64:<br>
<br>
<br>
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