[PATCH] D18072: Skeleton for the IR level pass to perform 64bit Integer Division

[Tom Stellard via llvm-commits]

tstellarAMD added inline comments.

================
Comment at: include/llvm/CodeGen/Passes.h:395-397
@@ -394,2 +394,5 @@
 
+  /// Lowers unsupported integer division.
+  extern char &IntegerDivisionID;
+
   /// MachineLoopInfo - This pass is a loop analysis pass.
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arsenm wrote:
> These parts touching generic code should be removed since it is a backend pass now. The IDs etc. declarations should be only in AMDGPU.h
Since this is a target specific pass the ID should be defined in AMDGPU.h like the other AMDGPU passes.

================
Comment at: include/llvm/CodeGen/Passes.h:652-653
@@ -648,1 +651,4 @@
 
+  /// Lower unsupported integer division
+  FunctionPass *createIntegerDivisionPass(const TargetMachine *TM);
+
----------------
This should go in AMDGPU.h too.

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Comment at: include/llvm/InitializePasses.h:152
@@ -151,2 +151,3 @@
 void initializeInstNamerPass(PassRegistry&);
+void initializeIntegerDivisionPass(PassRegistry&);
 void initializeInternalizePassPass(PassRegistry&);
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This in AMDGPU.h too.

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Comment at: include/llvm/LinkAllPasses.h:148-149
@@ -147,2 +147,4 @@
       (void) llvm::createJumpThreadingPass();
+      /*AMDGPU64bit*/
+      //(void) llvm::createIntegerDivisionPass(nullptr);
       (void) llvm::createUnifyFunctionExitNodesPass();
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I don't think this is needed.


http://reviews.llvm.org/D18072