[PATCH] D17747: TableGen: Check scheduling models for completeness

[Matthias Braun via llvm-commits]

Static checking should be more robust long-term than relying on the dynamic checks with the assert. This however means that instructions not supported by a CPU should be explicitely marked as unsupported. I just pushed a commit which lets you mark InstRW expressions as unsupported (on top of the existing support to mark scheduling resources as unsupported or whole instructions as not appearing in the scheduler). So it should be easy to get the list from tablegen and exclude the missing instructions with something like:

// Exclude micromips instructions
def : InstRW<[], (instregex ".*_MM$", ".*_MMR[0-9]$")> { let Unsupported = 1; }

Is that okay?

- Matthias

> On Mar 2, 2016, at 5:57 AM, Daniel Sanders <daniel.sanders at imgtec.com> wrote:
> 
> dsanders added inline comments.
> 
> ================
> Comment at: llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td:16
> @@ -15,3 +15,3 @@
> 
> -  let CompleteModel = 1;
> +  let CompleteModel = 0;
> }
> ----------------
> Hi,
> 
> I see you've changed our P5600 model to be incomplete but it is actually complete. We want the compiler to assert if it's asked to schedule an instruction that has no scheduling information since these instructions are not supposed to be possible on the P5600. This assertion will no longer occur with this change.
> 
> 
> Repository:
>  rL LLVM
> 
> http://reviews.llvm.org/D17747
> 
> 
>