[PATCH] D17747: TableGen: Check scheduling models for completeness

[Daniel Sanders via llvm-commits]

dsanders added inline comments.

================
Comment at: llvm/trunk/lib/Target/Mips/MipsScheduleP5600.td:16
@@ -15,3 +15,3 @@
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
 }
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Hi,

I see you've changed our P5600 model to be incomplete but it is actually complete. We want the compiler to assert if it's asked to schedule an instruction that has no scheduling information since these instructions are not supposed to be possible on the P5600. This assertion will no longer occur with this change.


Repository:
  rL LLVM

http://reviews.llvm.org/D17747