[PATCH] D17711: Fix for PR 26617 (disable scalar-to-vector conversions using direct moves for 32-bit targets)

[Nemanja Ivanovic via llvm-commits]

nemanjai updated this revision to Diff 49529.
nemanjai added a comment.

Added the test case that I forgot to svn add.


Repository:
  rL LLVM

http://reviews.llvm.org/D17711

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp
  test/CodeGen/PowerPC/pr26617.ll

Index: test/CodeGen/PowerPC/pr26617.ll
===================================================================
--- test/CodeGen/PowerPC/pr26617.ll
+++ test/CodeGen/PowerPC/pr26617.ll
@@ -0,0 +1,8 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s
+define i32 @test(<4 x i32> %v, i32 %elem) #0 {
+entry:
+  %vecext = extractelement <4 x i32> %v, i32 %elem
+  ret i32 %vecext
+}
+; CHECK: stxvw4x 34,
+; CHECK: lwzx 3,
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -557,7 +557,7 @@
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
       }
-      if (Subtarget.hasDirectMove()) {
+      if (Subtarget.hasDirectMove() && Subtarget.use64BitRegs()) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D17711.49529.patch
Type: text/x-patch
Size: 1135 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20160301/4543199b/attachment.bin>