[PATCH] D17711: Fix for PR 26617 (disable scalar-to-vector conversions using direct moves for 32-bit targets)

[Nemanja Ivanovic via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: hfinkel, kbarton, wschmidt.
nemanjai added a subscriber: llvm-commits.
nemanjai set the repository for this revision to rL LLVM.

When I implemented these conversions, I didn't consider what the results would be if someone attempted to build 32-bit applications on targets that have direct moves. This just disables the problematic conversions when 32-bit registers are used.

Repository:
  rL LLVM

http://reviews.llvm.org/D17711

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp

Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -557,7 +557,7 @@
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
         setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
       }
-      if (Subtarget.hasDirectMove()) {
+      if (Subtarget.hasDirectMove() && Subtarget.use64BitRegs()) {
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
         setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);


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