[PATCH] D17328: [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions

[Daniel Sanders via llvm-commits]

dsanders requested changes to this revision.
dsanders added a comment.

In addition to Simon's comments ...


================
Comment at: lib/Target/Mips/MicroMips32r6InstrInfo.td:580-581
@@ +579,4 @@
+class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd>;
+class MTHC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd>,
+                        HARDFLOAT;
+class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>;
----------------
As with the MFHC1 patch, we need a 64-bit FPU version of MTHC1.


http://reviews.llvm.org/D17328