[PATCH] D17160: AMDGPU/SI: Add llvm.amdgcn.mov.dpp intrinsic

[Tom Stellard via llvm-commits]

tstellarAMD updated this revision to Diff 47834.
tstellarAMD added a comment.

Add convergent attribute.


http://reviews.llvm.org/D17160

Files:
  include/llvm/IR/IntrinsicsAMDGPU.td
  lib/Target/AMDGPU/VIInstructions.td
  test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

Index: test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
@@ -0,0 +1,13 @@
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
+
+; VI-LABEL: {{^}}dpp_test:
+; VI: v_mov_b32 v0, v0, 1, -1, 1, 1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
+define void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
+  %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i1 1, i32 1, i32 1) #0
+  store i32 %tmp0, i32 addrspace(1)* %out
+  ret void
+}
+
+declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i1, i32, i32) #0
+
+attributes #0 = { nounwind readnone }
Index: lib/Target/AMDGPU/VIInstructions.td
===================================================================
--- lib/Target/AMDGPU/VIInstructions.td
+++ lib/Target/AMDGPU/VIInstructions.td
@@ -109,4 +109,15 @@
   (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
 >;
 
+//===----------------------------------------------------------------------===//
+// DPP Paterns
+//===----------------------------------------------------------------------===//
+
+def : Pat <
+  (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$bound_ctrl,
+                      imm:$bank_mask, imm:$row_mask),
+  (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i1imm $bound_ctrl),
+                       (as_i32imm $bank_mask), (as_i32imm $row_mask))
+>;
+
 } // End Predicates = [isVI]
Index: include/llvm/IR/IntrinsicsAMDGPU.td
===================================================================
--- include/llvm/IR/IntrinsicsAMDGPU.td
+++ include/llvm/IR/IntrinsicsAMDGPU.td
@@ -189,6 +189,12 @@
 // VI Intrinsics
 //===----------------------------------------------------------------------===//
 
+// llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <bound_ctrl> <bank_mask> <row_mask>
+def int_amdgcn_mov_dpp :
+  Intrinsic<[llvm_anyint_ty],
+            [LLVMMatchType<0>, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty,
+             llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
+
 def int_amdgcn_s_dcache_wb :
   GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">,
   Intrinsic<[], [], []>;


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