[PATCH] D17173: [X86] Update test cases that would be affected when X86FixupBWInsts is turned on.

[Kevin B. Smith via llvm-commits]

kbsmith1 created this revision.
kbsmith1 added reviewers: spatel, qcolombet.
kbsmith1 added a subscriber: llvm-commits.

This updates a small number of lit tests that will be affected when X86FixupBWInsts is turned on by default.  This simply
uses the internal switch to be sure to disable that optimization for these specific tests, so that they continue to test what they
are expecting to test.

http://reviews.llvm.org/D17173

Files:
  2008-06-13-NotVolatileLoadStore.ll
  MergeConsecutiveStores.ll
  avx512bw-intrinsics.ll
  half.ll
  merge-store-partially-alias-loads.ll
  return-ext.ll
  store-narrow.ll

Index: MergeConsecutiveStores.ll
===================================================================
--- MergeConsecutiveStores.ll
+++ MergeConsecutiveStores.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -addr-sink-using-gep=1 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=0 < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx -fixup-byte-word-insts=0 -addr-sink-using-gep=1 < %s | FileCheck %s
 
 %struct.A = type { i8, i8, i8, i8, i8, i8, i8, i8 }
 %struct.B = type { i32, i32, i32, i32, i32, i32, i32, i32 }
Index: half.ll
===================================================================
--- half.ll
+++ half.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false \
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c -asm-verbose=false -fixup-byte-word-insts=0 \
 ; RUN:   | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LIBCALL
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false \
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c -asm-verbose=false -fixup-byte-word-insts=0 \
 ; RUN:    | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-F16C
 
 define void @test_load_store(half* %in, half* %out) {
Index: merge-store-partially-alias-loads.ll
===================================================================
--- merge-store-partially-alias-loads.ll
+++ merge-store-partially-alias-loads.ll
@@ -1,6 +1,6 @@
 ; REQUIRES: asserts
-; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s
-; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s 2>&1 | FileCheck -check-prefix=DBGDAG %s
+; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -fixup-byte-word-insts=0 < %s | FileCheck -check-prefix=X86 %s
+; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -fixup-byte-word-insts=0 -debug-only=isel < %s 2>&1 | FileCheck -check-prefix=DBGDAG %s
 
 ; It's OK to merge the load / store of the first 2 components, but
 ; they must not be placed on the same chain after merging.
Index: store-narrow.ll
===================================================================
--- store-narrow.ll
+++ store-narrow.ll
@@ -1,6 +1,6 @@
 ; rdar://7860110
-; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=X64
-; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s -check-prefix=X32
+; RUN: llc -fixup-byte-word-insts=0 -asm-verbose=false < %s | FileCheck %s -check-prefix=X64
+; RUN: llc -fixup-byte-word-insts=0 -march=x86 -asm-verbose=false < %s | FileCheck %s -check-prefix=X32
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.2"
 
Index: avx512bw-intrinsics.ll
===================================================================
--- avx512bw-intrinsics.ll
+++ avx512bw-intrinsics.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
-; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=knl -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F-32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw -fixup-byte-word-insts=0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=knl -mattr=+avx512bw -fixup-byte-word-insts=0 | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F-32
 
 define i64 @test_pcmpeq_b(<64 x i8> %a, <64 x i8> %b) {
 ; AVX512BW-LABEL: test_pcmpeq_b:
Index: 2008-06-13-NotVolatileLoadStore.ll
===================================================================
--- 2008-06-13-NotVolatileLoadStore.ll
+++ 2008-06-13-NotVolatileLoadStore.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -march=x86 -fixup-byte-word-insts=0 | FileCheck %s
 ; These transforms are turned off for load volatiles and stores.
 ; Check that they weren't turned off for all loads and stores!
 ; CHECK-LABEL: f:
Index: return-ext.ll
===================================================================
--- return-ext.ll
+++ return-ext.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -fixup-byte-word-insts=0 -mtriple=i686-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -fixup-byte-word-insts=0 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
 
 
 @x = common global i32 0, align 4


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