[PATCH] D17000: [AArch64] Reduce number of callee-save save/restores.

[Geoff Berry via llvm-commits]

gberry added a comment.

Thanks Tim.  Are you okay with this going in, or should I wait for your additional test cases?  I'm fine with either.


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Comment at: lib/Target/AArch64/AArch64FrameLowering.cpp:757
@@ +756,3 @@
+  RegPairInfo &LastPair = RegPairs.back();
+  assert(AFI->getCalleeSavedStackSize() % 8 == 0);
+  LastPair.Offset = AFI->getCalleeSavedStackSize() / 8;
----------------
t.p.northover wrote:
> gberry wrote:
> > Not currently, no.  Maybe in a future change that combines the callee-save stack bump with the local variable stack bump.
> I'm not sure that would be allowed. The AAPCS says "Additionally, at any point at which memory is accessed via SP, the hardware requires that SP mod 16 = 0. The stack must be quad-word aligned."
> 
> It's a bit more complicated than that (it's configurable via SCTLR), but I think we should force anyone who wants to weaken that to think very hard about it.
I don't think the hypothetical future change that I'm thinking of would violate that rule.
If there was only a single instruction bumping the SP (for both the callee-save area and the local variable area), then it would be okay if the callee-save area was not 16-byte aligned as long as the "hole" was filled by local variable data so the single SP bump was 16-byte aligned.  There may be other reasons why this isn't workable though.  I'm also not sure it's worth the effort.


http://reviews.llvm.org/D17000