[llvm] r259791 - [Power PC] softening long double type
JF Bastien via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 4 07:42:50 PST 2016
Hi Petar,
This patch causes `make check` to fail when the ppc backend isn't built:
--
/b/build/slave/linux/build/src/src/work/llvm-out/./bin/llc
-mtriple=powerpc-unknown-linux-gnu -O0 <
/b/build/slave/linux/build/src/src/work/llvm/test/CodeGen/ppcf128sf.ll |
/b/build/slave/linux/build/src/src/work/llvm-out/./bin/FileCheck
/b/build/slave/linux/build/src/src/work/llvm/test/CodeGen/ppcf128sf.ll
--
Exit Code: 2
Command Output (stderr):
--
/b/build/slave/linux/build/src/src/work/llvm-out/./bin/llc: : error: unable
to get target for 'powerpc-unknown-linux-gnu', see --version and --triple.
FileCheck error: '-' is empty.
On Thu, Feb 4, 2016 at 6:43 AM, Petar Jovanovic via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
> Author: petarj
> Date: Thu Feb 4 08:43:50 2016
> New Revision: 259791
>
> URL: http://llvm.org/viewvc/llvm-project?rev=259791&view=rev
> Log:
> [Power PC] softening long double type
>
> This patch implements softening of long double type (ppcf128) on ppc32
> architecture and enables operations for this type for soft float.
>
> Patch by Strahinja Petrovic.
>
> Differential Revision: http://reviews.llvm.org/D15811
>
> Added:
> llvm/trunk/test/CodeGen/ppcf128sf.ll
> Modified:
> llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
>
> Modified: llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h?rev=259791&r1=259790&r2=259791&view=diff
>
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/RuntimeLibcalls.h Thu Feb 4 08:43:50
> 2016
> @@ -215,6 +215,8 @@ namespace RTLIB {
> FMAX_PPCF128,
>
> // CONVERSION
> + FPEXT_F32_PPCF128,
> + FPEXT_F64_PPCF128,
> FPEXT_F64_F128,
> FPEXT_F32_F128,
> FPEXT_F32_F64,
> @@ -296,27 +298,35 @@ namespace RTLIB {
> OEQ_F32,
> OEQ_F64,
> OEQ_F128,
> + OEQ_PPCF128,
> UNE_F32,
> UNE_F64,
> UNE_F128,
> + UNE_PPCF128,
> OGE_F32,
> OGE_F64,
> OGE_F128,
> + OGE_PPCF128,
> OLT_F32,
> OLT_F64,
> OLT_F128,
> + OLT_PPCF128,
> OLE_F32,
> OLE_F64,
> OLE_F128,
> + OLE_PPCF128,
> OGT_F32,
> OGT_F64,
> OGT_F128,
> + OGT_PPCF128,
> UO_F32,
> UO_F64,
> UO_F128,
> + UO_PPCF128,
> O_F32,
> O_F64,
> O_F128,
> + O_PPCF128,
>
> // MEMORY
> MEMCPY,
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=259791&r1=259790&r2=259791&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Feb 4
> 08:43:50 2016
> @@ -122,7 +122,7 @@ void TargetLowering::softenSetCCOperands
> SDValue &NewLHS, SDValue &NewRHS,
> ISD::CondCode &CCCode,
> SDLoc dl) const {
> - assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
> + assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT ==
> MVT::ppcf128)
> && "Unsupported setcc type!");
>
> // Expand into one or more soft-fp libcall(s).
> @@ -132,53 +132,65 @@ void TargetLowering::softenSetCCOperands
> case ISD::SETEQ:
> case ISD::SETOEQ:
> LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
> - (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
> + (VT == MVT::f64) ? RTLIB::OEQ_F64 :
> + (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
> break;
> case ISD::SETNE:
> case ISD::SETUNE:
> LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
> - (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
> + (VT == MVT::f64) ? RTLIB::UNE_F64 :
> + (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
> break;
> case ISD::SETGE:
> case ISD::SETOGE:
> LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
> - (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
> + (VT == MVT::f64) ? RTLIB::OGE_F64 :
> + (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
> break;
> case ISD::SETLT:
> case ISD::SETOLT:
> LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
> - (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
> + (VT == MVT::f64) ? RTLIB::OLT_F64 :
> + (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
> break;
> case ISD::SETLE:
> case ISD::SETOLE:
> LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
> - (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
> + (VT == MVT::f64) ? RTLIB::OLE_F64 :
> + (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
> break;
> case ISD::SETGT:
> case ISD::SETOGT:
> LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
> - (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
> + (VT == MVT::f64) ? RTLIB::OGT_F64 :
> + (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
> break;
> case ISD::SETUO:
> LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
> - (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
> + (VT == MVT::f64) ? RTLIB::UO_F64 :
> + (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
> break;
> case ISD::SETO:
> LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
> - (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
> + (VT == MVT::f64) ? RTLIB::O_F64 :
> + (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128;
> break;
> case ISD::SETONE:
> // SETONE = SETOLT | SETOGT
> LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
> - (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
> + (VT == MVT::f64) ? RTLIB::OLT_F64 :
> + (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
> LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
> - (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
> + (VT == MVT::f64) ? RTLIB::OGT_F64 :
> + (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
> break;
> case ISD::SETUEQ:
> LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
> - (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
> + (VT == MVT::f64) ? RTLIB::UO_F64 :
> + (VT == MVT::f128) ? RTLIB::UO_F64 : RTLIB::UO_PPCF128;
> LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
> - (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
> + (VT == MVT::f64) ? RTLIB::OEQ_F64 :
> + (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
> break;
> default:
> // Invert CC for unordered comparisons
> @@ -186,19 +198,23 @@ void TargetLowering::softenSetCCOperands
> switch (CCCode) {
> case ISD::SETULT:
> LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
> - (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
> + (VT == MVT::f64) ? RTLIB::OGE_F64 :
> + (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
> break;
> case ISD::SETULE:
> LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
> - (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
> + (VT == MVT::f64) ? RTLIB::OGT_F64 :
> + (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
> break;
> case ISD::SETUGT:
> LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
> - (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
> + (VT == MVT::f64) ? RTLIB::OLE_F64 :
> + (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
> break;
> case ISD::SETUGE:
> LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
> - (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
> + (VT == MVT::f64) ? RTLIB::OLT_F64 :
> + (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
> break;
> default: llvm_unreachable("Do not know how to soften this setcc!");
> }
>
> Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=259791&r1=259790&r2=259791&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
> +++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Thu Feb 4 08:43:50 2016
> @@ -231,6 +231,8 @@ static void InitLibcallNames(const char
> Names[RTLIB::COPYSIGN_F80] = "copysignl";
> Names[RTLIB::COPYSIGN_F128] = "copysignl";
> Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
> + Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq";
> + Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq";
> Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
> Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
> Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
> @@ -243,10 +245,10 @@ static void InitLibcallNames(const char
> Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
> Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
> Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
> - Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
> + Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos";
> Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
> Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
> - Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
> + Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod";
> Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
> Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
> Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
> @@ -259,7 +261,7 @@ static void InitLibcallNames(const char
> Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
> Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
> Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
> - Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
> + Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou";
> Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
> Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
> Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
> @@ -281,7 +283,7 @@ static void InitLibcallNames(const char
> Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
> Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
> Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
> - Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
> + Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq";
> Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
> Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
> Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
> @@ -296,7 +298,7 @@ static void InitLibcallNames(const char
> Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
> Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
> Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
> - Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
> + Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq";
> Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
> Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
> Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
> @@ -310,27 +312,35 @@ static void InitLibcallNames(const char
> Names[RTLIB::OEQ_F32] = "__eqsf2";
> Names[RTLIB::OEQ_F64] = "__eqdf2";
> Names[RTLIB::OEQ_F128] = "__eqtf2";
> + Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq";
> Names[RTLIB::UNE_F32] = "__nesf2";
> Names[RTLIB::UNE_F64] = "__nedf2";
> Names[RTLIB::UNE_F128] = "__netf2";
> + Names[RTLIB::UNE_PPCF128] = "__gcc_qne";
> Names[RTLIB::OGE_F32] = "__gesf2";
> Names[RTLIB::OGE_F64] = "__gedf2";
> Names[RTLIB::OGE_F128] = "__getf2";
> + Names[RTLIB::OGE_PPCF128] = "__gcc_qge";
> Names[RTLIB::OLT_F32] = "__ltsf2";
> Names[RTLIB::OLT_F64] = "__ltdf2";
> Names[RTLIB::OLT_F128] = "__lttf2";
> + Names[RTLIB::OLT_PPCF128] = "__gcc_qlt";
> Names[RTLIB::OLE_F32] = "__lesf2";
> Names[RTLIB::OLE_F64] = "__ledf2";
> Names[RTLIB::OLE_F128] = "__letf2";
> + Names[RTLIB::OLE_PPCF128] = "__gcc_qle";
> Names[RTLIB::OGT_F32] = "__gtsf2";
> Names[RTLIB::OGT_F64] = "__gtdf2";
> Names[RTLIB::OGT_F128] = "__gttf2";
> + Names[RTLIB::OGT_PPCF128] = "__gcc_qgt";
> Names[RTLIB::UO_F32] = "__unordsf2";
> Names[RTLIB::UO_F64] = "__unorddf2";
> Names[RTLIB::UO_F128] = "__unordtf2";
> + Names[RTLIB::UO_PPCF128] = "__gcc_qunord";
> Names[RTLIB::O_F32] = "__unordsf2";
> Names[RTLIB::O_F64] = "__unorddf2";
> Names[RTLIB::O_F128] = "__unordtf2";
> + Names[RTLIB::O_PPCF128] = "__gcc_qunord";
> Names[RTLIB::MEMCPY] = "memcpy";
> Names[RTLIB::MEMMOVE] = "memmove";
> Names[RTLIB::MEMSET] = "memset";
> @@ -446,9 +456,13 @@ RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT,
> return FPEXT_F32_F64;
> if (RetVT == MVT::f128)
> return FPEXT_F32_F128;
> + if (RetVT == MVT::ppcf128)
> + return FPEXT_F32_PPCF128;
> } else if (OpVT == MVT::f64) {
> if (RetVT == MVT::f128)
> return FPEXT_F64_F128;
> + else if (RetVT == MVT::ppcf128)
> + return FPEXT_F64_PPCF128;
> }
>
> return UNKNOWN_LIBCALL;
> @@ -698,27 +712,35 @@ static void InitCmpLibcallCCs(ISD::CondC
> CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
> CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
> CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
> + CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
> CCs[RTLIB::UNE_F32] = ISD::SETNE;
> CCs[RTLIB::UNE_F64] = ISD::SETNE;
> CCs[RTLIB::UNE_F128] = ISD::SETNE;
> + CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
> CCs[RTLIB::OGE_F32] = ISD::SETGE;
> CCs[RTLIB::OGE_F64] = ISD::SETGE;
> CCs[RTLIB::OGE_F128] = ISD::SETGE;
> + CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
> CCs[RTLIB::OLT_F32] = ISD::SETLT;
> CCs[RTLIB::OLT_F64] = ISD::SETLT;
> CCs[RTLIB::OLT_F128] = ISD::SETLT;
> + CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
> CCs[RTLIB::OLE_F32] = ISD::SETLE;
> CCs[RTLIB::OLE_F64] = ISD::SETLE;
> CCs[RTLIB::OLE_F128] = ISD::SETLE;
> + CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
> CCs[RTLIB::OGT_F32] = ISD::SETGT;
> CCs[RTLIB::OGT_F64] = ISD::SETGT;
> CCs[RTLIB::OGT_F128] = ISD::SETGT;
> + CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
> CCs[RTLIB::UO_F32] = ISD::SETNE;
> CCs[RTLIB::UO_F64] = ISD::SETNE;
> CCs[RTLIB::UO_F128] = ISD::SETNE;
> + CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
> CCs[RTLIB::O_F32] = ISD::SETEQ;
> CCs[RTLIB::O_F64] = ISD::SETEQ;
> CCs[RTLIB::O_F128] = ISD::SETEQ;
> + CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
> }
>
> /// NOTE: The TargetMachine owns TLOF.
> @@ -1250,10 +1272,17 @@ void TargetLoweringBase::computeRegister
>
> // ppcf128 type is really two f64's.
> if (!isTypeLegal(MVT::ppcf128)) {
> - NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
> - RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
> - TransformToType[MVT::ppcf128] = MVT::f64;
> - ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
> + if (isTypeLegal(MVT::f64)) {
> + NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
> + RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
> + TransformToType[MVT::ppcf128] = MVT::f64;
> + ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
> + } else {
> + NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
> + RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
> + TransformToType[MVT::ppcf128] = MVT::i128;
> + ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
> + }
> }
>
> // Decide how to handle f128. If the target does not have native f128
> support,
>
> Added: llvm/trunk/test/CodeGen/ppcf128sf.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ppcf128sf.ll?rev=259791&view=auto
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ppcf128sf.ll (added)
> +++ llvm/trunk/test/CodeGen/ppcf128sf.ll Thu Feb 4 08:43:50 2016
> @@ -0,0 +1,179 @@
> +; RUN: llc -mtriple=powerpc-unknown-linux-gnu -O0 < %s | FileCheck %s
> +
> + at ld = common global ppc_fp128 0xM00000000000000000000000000000000, align
> 16
> + at ld2 = common global ppc_fp128 0xM00000000000000000000000000000000, align
> 16
> + at d = common global double 0.000000e+00, align 8
> + at f = common global float 0.000000e+00, align 4
> + at i = common global i32 0, align 4
> + at ui = common global i32 0, align 4
> + at var = common global i8 0, align 1
> +
> +define void @foo() #0 {
> +entry:
> + %c = alloca ppc_fp128, align 16
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %add = fadd ppc_fp128 %0, %1
> + store ppc_fp128 %add, ppc_fp128* %c, align 16
> + %2 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %3 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %sub = fsub ppc_fp128 %2, %3
> + store ppc_fp128 %sub, ppc_fp128* %c, align 16
> + %4 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %5 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %mul = fmul ppc_fp128 %4, %5
> + store ppc_fp128 %mul, ppc_fp128* %c, align 16
> + %6 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %7 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %div = fdiv ppc_fp128 %6, %7
> + store ppc_fp128 %div, ppc_fp128* %c, align 16
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qadd
> + ; CHECK-LABEL: __gcc_qsub
> + ; CHECK-LABEL: __gcc_qmul
> + ; CHECK-LABEL: __gcc_qdiv
> +}
> +
> +define void @foo1() #0 {
> +entry:
> + %0 = load double, double* @d, align 8
> + %conv = fpext double %0 to ppc_fp128
> + store ppc_fp128 %conv, ppc_fp128* @ld, align 16
> + ret void
> +
> + ; CHECK-LABEL: __gcc_dtoq
> +}
> +
> +define void @foo2() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %conv = fptrunc ppc_fp128 %0 to double
> + store double %conv, double* @d, align 8
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qtod
> +}
> +
> +define void @foo3() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %conv = fptrunc ppc_fp128 %0 to float
> + store float %conv, float* @f, align 4
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qtos
> +}
> +
> +define void @foo4() #0 {
> +entry:
> + %0 = load i32, i32* @i, align 4
> + %conv = sitofp i32 %0 to ppc_fp128
> + store ppc_fp128 %conv, ppc_fp128* @ld, align 16
> + ret void
> +
> + ; CHECK-LABEL: __gcc_itoq
> +}
> +
> +define void @foo5() #0 {
> +entry:
> + %0 = load i32, i32* @ui, align 4
> + %conv = uitofp i32 %0 to ppc_fp128
> + store ppc_fp128 %conv, ppc_fp128* @ld, align 16
> + ret void
> +
> + ; CHECK-LABEL: __gcc_utoq
> +}
> +
> +define void @foo6() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %cmp = fcmp oeq ppc_fp128 %0, %1
> + %conv = zext i1 %cmp to i32
> + %conv1 = trunc i32 %conv to i8
> + store i8 %conv1, i8* @var, align 1
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qeq
> +}
> +
> +define void @foo7() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %cmp = fcmp une ppc_fp128 %0, %1
> + %conv = zext i1 %cmp to i32
> + %conv1 = trunc i32 %conv to i8
> + store i8 %conv1, i8* @var, align 1
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qne
> +}
> +
> +define void @foo8() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %cmp = fcmp ogt ppc_fp128 %0, %1
> + %conv = zext i1 %cmp to i32
> + %conv1 = trunc i32 %conv to i8
> + store i8 %conv1, i8* @var, align 1
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qgt
> +}
> +
> +define void @foo9() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %cmp = fcmp olt ppc_fp128 %0, %1
> + %conv = zext i1 %cmp to i32
> + %conv1 = trunc i32 %conv to i8
> + store i8 %conv1, i8* @var, align 1
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qlt
> +}
> +
> +define void @foo10() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %cmp = fcmp ole ppc_fp128 %0, %1
> + %conv = zext i1 %cmp to i32
> + %conv1 = trunc i32 %conv to i8
> + store i8 %conv1, i8* @var, align 1
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qle
> +}
> +
> +define void @foo11() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %cmp = fcmp une ppc_fp128 %0, %1
> + %conv = zext i1 %cmp to i32
> + %conv1 = trunc i32 %conv to i8
> + store i8 %conv1, i8* @var, align 1
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qunord
> +}
> +
> +define void @foo12() #0 {
> +entry:
> + %0 = load ppc_fp128, ppc_fp128* @ld, align 16
> + %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
> + %cmp = fcmp oge ppc_fp128 %0, %1
> + %conv = zext i1 %cmp to i32
> + %conv1 = trunc i32 %conv to i8
> + store i8 %conv1, i8* @var, align 1
> + ret void
> +
> + ; CHECK-LABEL: __gcc_qge
> +}
> +
> +attributes #0 = { "use-soft-float"="true" }
>
>
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