[PATCH] D16729: [X86][SSE] Add general 32-bit LOAD + VZEXT_MOVL support to EltsFromConsecutiveLoads

[Elena Demikhovsky via llvm-commits]

delena added inline comments.

================
Comment at: test/CodeGen/X86/merge-consecutive-loads-128.ll:335
@@ -335,4 +334,3 @@
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpinsrw $0, 6(%rdi), %xmm0, %xmm0
-; AVX-NEXT:    vpinsrw $1, 8(%rdi), %xmm0, %xmm0
+; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-NEXT:    retq
----------------
I think that in these architectures we pay additional cycle for switching from INT to FP. Can we use movd?

================
Comment at: test/CodeGen/X86/merge-consecutive-loads-256.ll:531
@@ -549,5 +530,3 @@
 ; AVX:       # BB#0:
-; AVX-NEXT:    vpinsrb $0, 4(%rdi), %xmm0, %xmm0
-; AVX-NEXT:    vpinsrb $1, 5(%rdi), %xmm0, %xmm0
-; AVX-NEXT:    vpinsrb $3, 7(%rdi), %xmm0, %xmm0
+; AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; AVX-NEXT:    retq
----------------
this instruction (movss) reads 4 bytes from memory. Does it require 4 bytes alignment?


Repository:
  rL LLVM

http://reviews.llvm.org/D16729