[PATCH] D16787: [AArch64] Allocate the modified and used regs once per function.

[Chad Rosier via llvm-commits]

mcrosier created this revision.
mcrosier added reviewers: MatzeB, gberry, t.p.northover, jmolloy.
mcrosier added subscribers: llvm-commits, junbuml, mssimpso, haicheng, bmakam.
Herald added subscribers: rengolin, aemerson.

Rather than once per load/store in the function.  NFC, but hopefully this has a non-trivial improvement on compile-time.

 Chad

http://reviews.llvm.org/D16787

Files:
  lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
===================================================================
--- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -88,6 +88,9 @@
   const TargetRegisterInfo *TRI;
   const AArch64Subtarget *Subtarget;
 
+  // Track which registers have been modified and used.
+  BitVector ModifiedRegs, UsedRegs;
+
   // Scan the instructions looking for a load/store that can be combined
   // with the current instruction into a load/store pair.
   // Return the matching instruction if one is found, else MBB->end().
@@ -1015,9 +1018,8 @@
 
   // Track which registers have been modified and used between the first insn
   // and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
 
   for (unsigned Count = 0; MBBI != E && Count < Limit;) {
     --MBBI;
@@ -1096,9 +1098,8 @@
 
   // Track which registers have been modified and used between the first insn
   // (inclusive) and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
 
   // Remember any instructions that read/write memory between FirstMI and MI.
   SmallVector<MachineInstr *, 4> MemInsns;
@@ -1378,9 +1379,8 @@
 
   // Track which registers have been modified and used between the first insn
   // (inclusive) and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
   ++MBBI;
   for (; MBBI != E; ++MBBI) {
     MachineInstr *MI = MBBI;
@@ -1428,9 +1428,8 @@
 
   // Track which registers have been modified and used between the first insn
   // (inclusive) and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
   --MBBI;
   for (; MBBI != B; --MBBI) {
     MachineInstr *MI = MBBI;
@@ -1784,6 +1783,10 @@
   TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
   TRI = Subtarget->getRegisterInfo();
 
+  // Resize the modified and used register bitfield trackers.
+  ModifiedRegs.resize(TRI->getNumRegs());
+  UsedRegs.resize(TRI->getNumRegs());
+
   bool Modified = false;
   bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
   for (auto &MBB : Fn)


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