[llvm] r259427 - [X86][AVX512] Add support for AVX512 VMOVSD/VMOVSS shuffle decoding
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 1 14:26:29 PST 2016
Author: rksimon
Date: Mon Feb 1 16:26:28 2016
New Revision: 259427
URL: http://llvm.org/viewvc/llvm-project?rev=259427&view=rev
Log:
[X86][AVX512] Add support for AVX512 VMOVSD/VMOVSS shuffle decoding
Modified:
llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll
Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=259427&r1=259426&r2=259427&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original)
+++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Mon Feb 1 16:26:28 2016
@@ -652,22 +652,26 @@ bool llvm::EmitAnyX86InstComments(const
case X86::MOVSDrr:
case X86::VMOVSDrr:
+ case X86::VMOVSDZrr:
Src2Name = getRegName(MI->getOperand(2).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
case X86::MOVSDrm:
case X86::VMOVSDrm:
+ case X86::VMOVSDZrm:
DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
case X86::MOVSSrr:
case X86::VMOVSSrr:
+ case X86::VMOVSSZrr:
Src2Name = getRegName(MI->getOperand(2).getReg());
Src1Name = getRegName(MI->getOperand(1).getReg());
// FALL THROUGH.
case X86::MOVSSrm:
case X86::VMOVSSrm:
+ case X86::VMOVSSZrm:
DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
break;
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll?rev=259427&r1=259426&r2=259427&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll Mon Feb 1 16:26:28 2016
@@ -74,20 +74,10 @@ define <4 x float> @merge_4f32_f32_3zuu(
; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-NEXT: retq
;
-; AVX1-LABEL: merge_4f32_f32_3zuu:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: merge_4f32_f32_3zuu:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; AVX2-NEXT: retq
-;
-; AVX512F-LABEL: merge_4f32_f32_3zuu:
-; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovss 12(%rdi), %xmm0
-; AVX512F-NEXT: retq
+; AVX-LABEL: merge_4f32_f32_3zuu:
+; AVX: # BB#0:
+; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-NEXT: retq
%ptr0 = getelementptr inbounds float, float* %ptr, i64 3
%val0 = load float, float* %ptr0
%res0 = insertelement <4 x float> undef, float %val0, i32 0
@@ -122,26 +112,12 @@ define <4 x float> @merge_4f32_f32_34z6(
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1,0]
; SSE-NEXT: retq
;
-; AVX1-LABEL: merge_4f32_f32_34z6:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX1-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1,0]
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: merge_4f32_f32_34z6:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX2-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1,0]
-; AVX2-NEXT: retq
-;
-; AVX512F-LABEL: merge_4f32_f32_34z6:
-; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; AVX512F-NEXT: vmovss 24(%rdi), %xmm1
-; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1,0]
-; AVX512F-NEXT: retq
+; AVX-LABEL: merge_4f32_f32_34z6:
+; AVX: # BB#0:
+; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
+; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1,0]
+; AVX-NEXT: retq
%ptr0 = getelementptr inbounds float, float* %ptr, i64 3
%ptr1 = getelementptr inbounds float, float* %ptr, i64 4
%ptr3 = getelementptr inbounds float, float* %ptr, i64 6
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll?rev=259427&r1=259426&r2=259427&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-256.ll Mon Feb 1 16:26:28 2016
@@ -50,20 +50,10 @@ define <4 x double> @merge_4f64_f64_2345
}
define <4 x double> @merge_4f64_f64_3zuu(double* %ptr) nounwind uwtable noinline ssp {
-; AVX1-LABEL: merge_4f64_f64_3zuu:
-; AVX1: # BB#0:
-; AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: merge_4f64_f64_3zuu:
-; AVX2: # BB#0:
-; AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
-; AVX2-NEXT: retq
-;
-; AVX512F-LABEL: merge_4f64_f64_3zuu:
-; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovsd 24(%rdi), %xmm0
-; AVX512F-NEXT: retq
+; AVX-LABEL: merge_4f64_f64_3zuu:
+; AVX: # BB#0:
+; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX-NEXT: retq
%ptr0 = getelementptr inbounds double, double* %ptr, i64 3
%val0 = load double, double* %ptr0
%res0 = insertelement <4 x double> undef, double %val0, i32 0
@@ -121,7 +111,7 @@ define <4 x double> @merge_4f64_f64_34z6
; AVX512F-LABEL: merge_4f64_f64_34z6:
; AVX512F: # BB#0:
; AVX512F-NEXT: vmovdqu 24(%rdi), %xmm0
-; AVX512F-NEXT: vmovsd 48(%rdi), %xmm1
+; AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX512F-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
; AVX512F-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
@@ -315,10 +305,10 @@ define <8 x float> @merge_8f32_f32_1u3u5
;
; AVX512F-LABEL: merge_8f32_f32_1u3u5zu8:
; AVX512F: # BB#0:
-; AVX512F-NEXT: vmovss 32(%rdi), %xmm0
-; AVX512F-NEXT: vmovss 20(%rdi), %xmm1
+; AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX512F-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512F-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[1,0]
-; AVX512F-NEXT: vmovss 4(%rdi), %xmm1
+; AVX512F-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX512F-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
; AVX512F-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
; AVX512F-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll?rev=259427&r1=259426&r2=259427&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-512.ll Mon Feb 1 16:26:28 2016
@@ -95,11 +95,11 @@ define <8 x double> @merge_8f64_f64_12zz
define <8 x double> @merge_8f64_f64_1u3u5zu8(double* %ptr) nounwind uwtable noinline ssp {
; ALL-LABEL: merge_8f64_f64_1u3u5zu8:
; ALL: # BB#0:
-; ALL-NEXT: vmovsd 40(%rdi), %xmm0
+; ALL-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; ALL-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
; ALL-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
-; ALL-NEXT: vmovsd 8(%rdi), %xmm1
-; ALL-NEXT: vmovsd 24(%rdi), %xmm2
+; ALL-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
+; ALL-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; ALL-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; ALL-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
; ALL-NEXT: retq
@@ -249,7 +249,7 @@ define <16 x float> @merge_16f32_f32_0uu
; ALL-LABEL: merge_16f32_f32_0uu3zzuuuuuzCuEF:
; ALL: # BB#0:
; ALL-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
-; ALL-NEXT: vmovss 48(%rdi), %xmm1
+; ALL-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; ALL-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; ALL-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; ALL-NEXT: vmovupd (%rdi), %xmm1
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