[PATCH] D16434: Fix ARM load/store opt live reg computing

[Weiming Zhao via llvm-commits]

weimingz updated the summary for this revision.
weimingz updated this revision to Diff 45734.
weimingz added a comment.

At first, I thought LR was just a corner case that ld/st opt didn't handled correctly.
Then, I find another case where R4 is used in exiting BB and not restored.

Before ld/st opt pass:

BB#3: derived from LLVM BB %if.end

  Live Ins: %R0 %R1 %R2 %R3 %R12 %LR %R7 %R5 %R4
  Predecessors according to CFG: BB#2 BB#1

t2STRi12 %R2<kill>, %http://reviews.llvm.org/diffusion/L/, 20, pred:14, pred:%noreg; mem:ST4[%21]
	t2STRi12 %R3<kill>, %http://reviews.llvm.org/diffusion/L/, 24, pred:14, pred:%noreg; mem:ST4[%22]
	t2STRi12 %R12<kill>, %http://reviews.llvm.org/diffusion/L/, 28, pred:14, pred:%noreg; mem:ST4[%23]
	t2STRi12 %R0<kill>, %http://reviews.llvm.org/diffusion/L/<kill>, 32, pred:14, pred:%noreg; mem:ST4[%24]
	tBX_RET pred:14, pred:%noreg

After ld/st opt pass:
BB#3: derived from LLVM BB %if.end

  Live Ins: %R0 %R1 %R2 %R3 %R12 %LR %R7 %R5 %R4
  Predecessors according to CFG: BB#2 BB#1

%R4<def> = t2ADDri %http://reviews.llvm.org/diffusion/L/, 20, pred:14, pred:%noreg, opt:%noreg
	t2STMIA %R4<kill>, pred:14, pred:%noreg, %R2<kill>, %R3<kill>, %R12<kill>   ==> R4 is clobbed
	t2STRi12 %R0<kill>, %http://reviews.llvm.org/diffusion/L/<kill>, 32, pred:14, pred:%noreg; mem:ST4[%24]
	tBX_RET pred:14, pred:%noreg


Repository:
  rL LLVM

http://reviews.llvm.org/D16434

Files:
  lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Index: lib/Target/ARM/ARMLoadStoreOptimizer.cpp
===================================================================
--- lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -553,6 +553,17 @@
   if (!LiveRegsValid) {
     LiveRegs.init(TRI);
     LiveRegs.addLiveOuts(&MBB, true);
+    auto MI = MBB.getLastNonDebugInstr();
+    // For exiting BB, we need to initially mark callee saved regs as live-out
+    //  because passes like shrink-wrap may move the reg restoring around.
+    if (MI != MBB.end() &&
+        (MI->getOpcode() == ARM::BX_RET || MI->getOpcode() == ARM::tBX_RET ||
+         MI->getOpcode() == ARM::MOVPCLR)) {
+      const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(MBB.getParent());
+      while (*CSRegs)
+        LiveRegs.addReg(*CSRegs++);
+    }
+
     LiveRegPos = MBB.end();
     LiveRegsValid = true;
   }


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