[PATCH] D16434: Fix ARM load/store opt live reg computing

[Weiming Zhao via llvm-commits]

weimingz added a comment.

In http://reviews.llvm.org/D16434#333667, @MatzeB wrote:

> This patch looks like fixing a symptom rather than the root cause. Shouldn't BX_RET simply have an implicit use operand for LR? So this would rather need fixing where BX_RET is constructed.


Yes, I tried to add a use in td file like:
let isReturn = 1, isTerminator = 1, isBarrier = 1, Uses = [LR] in {

  def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
                   [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;

Then I got an error like "use of undefined register LR". Any suggestions?

Thanks


Repository:
  rL LLVM

http://reviews.llvm.org/D16434