[PATCH] D16141: [TableGen] Fix sort order of asm operand classes

Daniel Sanders via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 19 07:40:13 PST 2016


dsanders added a subscriber: dsanders.
dsanders added a comment.

> If I reverse this comparison I get 8 test failures spread across the AArch64, Mips and X86 backends, so I have left it in until those backends can be fixed.


The Mips failure is that there's a choice of two accurate error messages and changing the order of these matchables changes which one is emitted. Of the two, the current one is preferable (since it slightly exaggerates its expected values to accommodate both possible matches) but ideally we would be able to emit multiple reasons for a failed match (e.g. 'expected either unsigned 5 bit immediate or values 32..63').

The ValueName is the only available tie breaker at the moment. Superclasses could be used to produce the right effect but it seems wrong to declare one a superclass of the other when the accepted values are distinct sets. At the moment, I'm thinking we should just make the priority explicit using something similar to the AddedComplexity field from instruction selection. Do you agree?


http://reviews.llvm.org/D16141





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