[PATCH] D16233: AMDGPU/SI: Promote i1 SETCC operations

[Matt Arsenault via llvm-commits]

arsenm added a comment.

In http://reviews.llvm.org/D16233#329609, @tstellarAMD wrote:

> In http://reviews.llvm.org/D16233#328073, @arsenm wrote:
>
> > From the testcase, I don't see why promotion would be necessary here
>
>
> The basic block order is swapped by SelectionDAG, so an i1 xor is inserted before the branch instruction.  This is optimized to an i1 setcc instruction by the DAGCombine.  This isn't an issue now, because SIISelLowering::LowerBRCOND was folding these into the branch intrinsic, but it will be an issue when we switch to uniform branching.


Can you swap the block order and insert the xor here for the same effect so the DAG builder doesn't do this?


http://reviews.llvm.org/D16233