[PATCH] D16233: AMDGPU/SI: Promote i1 SETCC operations

[Tom Stellard via llvm-commits]

tstellarAMD added a comment.

In http://reviews.llvm.org/D16233#328073, @arsenm wrote:

> From the testcase, I don't see why promotion would be necessary here


The basic block order is swapped by SelectionDAG, so an i1 xor is inserted before the branch instruction.  This is optimized to an i1 setcc instruction by the DAGCombine.  This isn't an issue now, because SIISelLowering::LowerBRCOND was folding these into the branch intrinsic, but it will be an issue when we switch to uniform branching.


http://reviews.llvm.org/D16233