[PATCH] D16110: [Power9] Implement new vsx instructions: quad-precision move, fp-arithmetic

[Chuang-Yu Cheng via llvm-commits]

cycheng marked 7 inline comments as done.

================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1224
@@ +1223,3 @@
+  def XSCPSGNQP : XForm_18<63, 100,
+                      (outs vrrc:$vT), (ins vrrc:$vA, vrrc:$vB),
+                      "xscpsgnqp $vT, $vA, $vB", IIC_VecFP,
----------------
nemanjai wrote:
> These are VSX instructions, are they not? Why the VMX register class?
> I imagine this is because we have never supported f128 in the VSX registers. However, I don't believe the right course of action is to put these in the VMX registers and thereby be able to allocate only half the registers.
> We need to do a bit more to implement support for f128.
> I imagine that we can add the type to the VSRC class, but I haven't thought about it much.
> 
> Of course, we can simply put in FIXME's to deal with the types later.
Yes, but according to spec, it seems to be the same VMX registers.

`Power ISA 3.0` //7.2.1.2 Vector Registers//, p.386:
  - When VSX is implemented, the 32 VRs are mapped to VSRs 32-63
  - All instructions that operate on a VR are redefined to operate on the corresponding VSR.

If we read the instruction pesudo code, e.g. //xscpsgnqp VRT,VRA,VRB//
```
src1 = VSR[VRA+32] & 0x8000...
src2 = VSR[VRB+32] & 0x7FFF...
VSR[VRT+32] = src1 | src2
```

Only half of VSX registers are used, that's why spec only use 5 bits for register encoding.

So that's why I choose 'vrrc'.


http://reviews.llvm.org/D16110