[PATCH] D15477: [X86][AVX] Only shuffle the lower half of vectors if the upper half is undefined

[Simon Pilgrim via llvm-commits]

RKSimon added inline comments.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:22587
@@ +22586,3 @@
+  // vector_shuffle <X, X, X, X, u, u, u, u> or <X, X, u, u>
+  if (isUndefInRange(SVOp->getMask(), HalfNumElems, HalfNumElems)) {
+    // If the shuffle only uses the lower halves of the inputs,
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delena wrote:
> Hi Simon,
> 
> Why you are doing this in PerformShuffleCombine and not in the lowerVectorShuffle()? As far as I understand, we call "combine" in order to combine multiple nodes. In this case, you just optimize one node.
Mainly because this has more in common with the 2 extract/insert patterns above than the canonicalization in lowerVectorShuffle. But I'm happy to move it (and the other 2?) there if you think necessary.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:22611
@@ +22610,3 @@
+      SDValue V = DAG.getVectorShuffle(HalfVT, dl, Half1, Half2, HalfMask);
+      SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
+      return DCI.CombineTo(N, InsV);
----------------
congh wrote:
> Can we always guarantee that V is a 128-bit vector?  I remember VECTOR_SHUFFLE can have different types for its operands and result.
At this stage yes we know that the result and operands are all 256-bit vectors - shuffles in the DAG have to have consistent types. I did add the FIXME comment mentioning that this could be generalised to 256 or 512 bit vectors though - at that point it would need to be refactored.


Repository:
  rL LLVM

http://reviews.llvm.org/D15477