[llvm] r255010 - [AArch64] Add ARMv8.2-A FP16 vector instructions

[Oliver Stannard via llvm-commits]

Good catch, fixed in 255113.

Oliver

> -----Original Message-----
> From: Ahmed Bougacha [mailto:ahmed.bougacha at gmail.com]
> Sent: 08 December 2015 19:03
> To: Oliver Stannard
> Cc: llvm-commits at lists.llvm.org
> Subject: Re: [llvm] r255010 - [AArch64] Add ARMv8.2-A FP16 vector
> instructions
> 
> On Tue, Dec 8, 2015 at 4:16 AM, Oliver Stannard via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
> > Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> > URL: http://llvm.org/viewvc/llvm-
> project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=255010&r1
> =255009&r2=255010&view=diff
> >
> ==========================================================================
> ====
> > --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
> > +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Tue Dec  8
> 06:16:10 2015
> > @@ -6712,6 +6853,21 @@ multiclass SIMDFPIndexed<bit U, bits<4>
> >      let Inst{21} = 0;
> >    }
> >
> > +  let Predicates = [HasNEON, HasFullFP16] in {
> > +  def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b00, opc,
> > +                                      FPR16Op, FPR16Op, V128,
> VectorIndexH,
> 
> Hey Oliver, should this be V128_lo, like v4i16/v8i16?
> 
> > +                                      asm, ".h", "", "", ".h",
> > +    [(set (f16 FPR16Op:$Rd),
> > +          (OpNode (f16 FPR16Op:$Rn),
> > +                  (f16 (vector_extract (v8f16 V128:$Rm),
> > +                                       VectorIndexH:$idx))))]> {
> > +    bits<3> idx;
> > +    let Inst{11} = idx{2};
> > +    let Inst{21} = idx{1};
> > +    let Inst{20} = idx{0};
> > +  }
> > +  } // Predicates = [HasNEON, HasFullFP16]
> > +
> >    def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
> >                                        FPR32Op, FPR32Op, V128,
> VectorIndexS,
> >                                        asm, ".s", "", "", ".s",
> > @@ -6816,6 +6993,16 @@ multiclass SIMDFPIndexedTied<bit U, bits
> >      let Inst{21} = 0;
> >    }
> >
> > +  let Predicates = [HasNEON, HasFullFP16] in {
> > +  def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b00, opc,
> > +                                      FPR16Op, FPR16Op, V128,
> VectorIndexH,
> 
> Ditto.
> 
> -Ahmed
> 
> > +                                      asm, ".h", "", "", ".h", []> {
> > +    bits<3> idx;
> > +    let Inst{11} = idx{2};
> > +    let Inst{21} = idx{1};
> > +    let Inst{20} = idx{0};
> > +  }
> > +  } // Predicates = [HasNEON, HasFullFP16]
> >
> >    def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
> >                                        FPR32Op, FPR32Op, V128,
> VectorIndexS,