[PATCH] D15372: Remaining TblGen patterns for extract vector element for legal types on PPC

[Nemanja Ivanovic via llvm-commits]

nemanjai added inline comments.

================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1276
@@ -1277,3 +1275,3 @@
 */
-def MovesFromVSR {
+def VectorExtractions {
   // Doubleword extraction
----------------
Just changed the name of this to reflect what the definition actually contains. Not all extractions are done with moves from VSRs (namely, the floating point ones).

================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1499
@@ -1436,3 +1498,3 @@
                         sub_64));
-  dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 60),
+  dag BE_VHALF_SHIFT = (EXTRACT_SUBREG (RLDICR (ANDC8 (LI8 3), $Idx), 4, 59),
                                        sub_32);
----------------
This was a bug originally. This is meant to be a shift left by 4 bits. I don't think there was any functional impact of this bug, but I corrected it for clarity and consistency.


Repository:
  rL LLVM

http://reviews.llvm.org/D15372