[PATCH] D15372: Remaining TblGen patterns for extract vector element for legal types on PPC

[Nemanja Ivanovic via llvm-commits]

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With the introduction of VSX (P7) and subsequently direct moves (P8), we have legalized the extract vector element operation for various types. However, the TblGen patterns were not introduced to handle variable index for the element being extracted. This meant that the back end would crash when trying to match a DAG node that has the extract_vector_elt with a variable as the last operand and one of the legal types.

This patch eliminates those crashes and performs the operation with an optimal instruction sequence (avoiding stack stores and reloads).

Repository:
  rL LLVM

http://reviews.llvm.org/D15372

Files:
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
  test/CodeGen/PowerPC/variable_elem_vec_extracts.ll

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