[PATCH] D15110: Fixed a bug in FP logic operation lowering on AVX-512

[Manman Ren via llvm-commits]

manmanren added a subscriber: manmanren.
manmanren added a comment.

FP logic instructions are supported in DQ extension on AVX-512 target.
We can use integer operations instead.
Added tests.
I also enabled FABS in this patch in order to check ANDPS.

--> Is it possible to separate enabling of FABS?

Cheers,
Manman


================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:26171
@@ +26170,3 @@
+  if (VT.is512BitVector() && !Subtarget->hasDQI()) {
+    // VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention
+    // These logic operations may be executed in the integer domain.
----------------
Nit: period at end.

================
Comment at: ../lib/Target/X86/X86ISelLowering.cpp:26182
@@ +26181,3 @@
+      default:
+        assert("Unexpected FP logic op");
+        break;
----------------
Nit: llvm_unreachable?


Repository:
  rL LLVM

http://reviews.llvm.org/D15110