[PATCH] D14883: [PPC]: Add a subtarget feature for integer add/load fusion. NFC

[Eric Christopher via llvm-commits]

Hi Kyle,

I've gone ahead and approved/committed this, but don't forget to add
llvm-commits to the patch when you create the phab link :)

-eric

On Fri, Nov 20, 2015 at 12:59 PM Kyle Butt <kyle+llvm at iteratee.net> wrote:

> iteratee created this revision.
> iteratee added a reviewer: echristo.
>
> Power8 and later support fusing addis/addi and addis/ld instruction
> pairs that use the same register to execute as a single instruction.
> Non-Functional Change
>
> http://reviews.llvm.org/D14883
>
> Files:
>   lib/Target/PowerPC/PPC.td
>   lib/Target/PowerPC/PPCSubtarget.cpp
>   lib/Target/PowerPC/PPCSubtarget.h
>
> Index: lib/Target/PowerPC/PPCSubtarget.h
> ===================================================================
> --- lib/Target/PowerPC/PPCSubtarget.h
> +++ lib/Target/PowerPC/PPCSubtarget.h
> @@ -119,6 +119,7 @@
>    bool HasPartwordAtomics;
>    bool HasDirectMove;
>    bool HasHTM;
> +  bool HasFusion;
>
>    /// When targeting QPX running a stock PPC64 Linux kernel where the
> stack
>    /// alignment has not been changed, we need to keep the 16-byte
> alignment
> @@ -254,6 +255,7 @@
>      return 16;
>    }
>    bool hasHTM() const { return HasHTM; }
> +  bool hasFusion() const { return HasFusion; }
>
>    const Triple &getTargetTriple() const { return TargetTriple; }
>
> Index: lib/Target/PowerPC/PPCSubtarget.cpp
> ===================================================================
> --- lib/Target/PowerPC/PPCSubtarget.cpp
> +++ lib/Target/PowerPC/PPCSubtarget.cpp
> @@ -100,6 +100,7 @@
>    HasDirectMove = false;
>    IsQPXStackUnaligned = false;
>    HasHTM = false;
> +  HasFusion = false;
>  }
>
>  void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
> Index: lib/Target/PowerPC/PPC.td
> ===================================================================
> --- lib/Target/PowerPC/PPC.td
> +++ lib/Target/PowerPC/PPC.td
> @@ -137,6 +137,8 @@
>                                    "Enable Hardware Transactional Memory
> instructions">;
>  def FeatureMFTB   : SubtargetFeature<"", "FeatureMFTB", "true",
>                                          "Implement mftb using the mfspr
> instruction">;
> +def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
> +                                     "Target supports add/load integer
> fusion.">;
>
>  def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
>    "Treat vector data stream cache control instructions as deprecated">;
> @@ -168,7 +170,8 @@
>         FeatureMFTB, DeprecatedDST];
>    list<SubtargetFeature> Power8SpecificFeatures =
>        [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
> -       FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];
> +       FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,
> +       FeatureFusion];
>    list<SubtargetFeature> Power8FeatureList =
>        !listconcat(Power7FeatureList, Power8SpecificFeatures);
>  }
>
>
>
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