<div dir="ltr">Hi Kyle,<div><br></div><div>I've gone ahead and approved/committed this, but don't forget to add llvm-commits to the patch when you create the phab link :)</div><div><br></div><div>-eric<br><br><div class="gmail_quote"><div dir="ltr">On Fri, Nov 20, 2015 at 12:59 PM Kyle Butt <<a href="mailto:kyle%2Bllvm@iteratee.net">kyle+llvm@iteratee.net</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">iteratee created this revision.<br>
iteratee added a reviewer: echristo.<br>
<br>
Power8 and later support fusing addis/addi and addis/ld instruction<br>
pairs that use the same register to execute as a single instruction.<br>
Non-Functional Change<br>
<br>
<a href="http://reviews.llvm.org/D14883" rel="noreferrer" target="_blank">http://reviews.llvm.org/D14883</a><br>
<br>
Files:<br>
lib/Target/PowerPC/PPC.td<br>
lib/Target/PowerPC/PPCSubtarget.cpp<br>
lib/Target/PowerPC/PPCSubtarget.h<br>
<br>
Index: lib/Target/PowerPC/PPCSubtarget.h<br>
===================================================================<br>
--- lib/Target/PowerPC/PPCSubtarget.h<br>
+++ lib/Target/PowerPC/PPCSubtarget.h<br>
@@ -119,6 +119,7 @@<br>
bool HasPartwordAtomics;<br>
bool HasDirectMove;<br>
bool HasHTM;<br>
+ bool HasFusion;<br>
<br>
/// When targeting QPX running a stock PPC64 Linux kernel where the stack<br>
/// alignment has not been changed, we need to keep the 16-byte alignment<br>
@@ -254,6 +255,7 @@<br>
return 16;<br>
}<br>
bool hasHTM() const { return HasHTM; }<br>
+ bool hasFusion() const { return HasFusion; }<br>
<br>
const Triple &getTargetTriple() const { return TargetTriple; }<br>
<br>
Index: lib/Target/PowerPC/PPCSubtarget.cpp<br>
===================================================================<br>
--- lib/Target/PowerPC/PPCSubtarget.cpp<br>
+++ lib/Target/PowerPC/PPCSubtarget.cpp<br>
@@ -100,6 +100,7 @@<br>
HasDirectMove = false;<br>
IsQPXStackUnaligned = false;<br>
HasHTM = false;<br>
+ HasFusion = false;<br>
}<br>
<br>
void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {<br>
Index: lib/Target/PowerPC/PPC.td<br>
===================================================================<br>
--- lib/Target/PowerPC/PPC.td<br>
+++ lib/Target/PowerPC/PPC.td<br>
@@ -137,6 +137,8 @@<br>
"Enable Hardware Transactional Memory instructions">;<br>
def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true",<br>
"Implement mftb using the mfspr instruction">;<br>
+def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",<br>
+ "Target supports add/load integer fusion.">;<br>
<br>
def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true",<br>
"Treat vector data stream cache control instructions as deprecated">;<br>
@@ -168,7 +170,8 @@<br>
FeatureMFTB, DeprecatedDST];<br>
list<SubtargetFeature> Power8SpecificFeatures =<br>
[DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,<br>
- FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];<br>
+ FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,<br>
+ FeatureFusion];<br>
list<SubtargetFeature> Power8FeatureList =<br>
!listconcat(Power7FeatureList, Power8SpecificFeatures);<br>
}<br>
<br>
<br>
</blockquote></div></div></div>